David Raeman
ea7c48ad38
It is, in principle, possible to use an external clock to synchronize N3x0 devices in frequency, and then use a GPSDO for a coarse time synchronization. This use case is deliberately not supported, as the GPSDO PPS signal and the external clock signal are by definition not matched, which will remove any guarantees on time/phase alignment. Because there are certain, niche use cases where the lack of phase alignment is acceptable, but only an external clock is available (no shared external PPS), usage of GPS for generating a PPS signal may be fine. This patch does not enable the usage of this combination out of the box, but adds comments and an update to the manual to explain the risks of this combination, and how to enable it (by patching MPM). Original-commit: 76e004db07a3714139e64ff396a81b90c372b2bb
328 lines
11 KiB
Verilog
328 lines
11 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//
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// Copyright 2017 Ettus Research, A National Instruments Company
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: n3xx_clocking.v
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//
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// Purpose:
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//
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// First, instantiate clock input buffers on all clocks to provide termination
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// for the PCB traces. This file also includes the MMCM for generating meas_clk at
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// specific rates and a global buffer for the reference clock to be able to use it
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// directly within and outside of this module.
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//
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// Second, PPS inputs from the back panel (called external) and the GPSDO are captured by
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// the Reference Clock. Selection is performed amongst these and the internally-generated
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// options.
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//
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// NOTE: BUFGs are NOT instantiated on the following clocks, denoted by the _buf suffix:
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// wr_refclk_buf, netclk_buf, gige_refclk_buf, xgige_refclk_buf
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//
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//////////////////////////////////////////////////////////////////////
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module n3xx_clocking (
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// Input buffers for clocks
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input enable_ref_clk_async, // enables the ref_clk BUFG (driven async to ref_clk)
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input FPGA_REFCLK_P, FPGA_REFCLK_N,
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output ref_clk,
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input WB_20MHz_P, WB_20MHz_N,
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output wr_refclk_buf,
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input NETCLK_REF_P, NETCLK_REF_N,
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output netclk_buf,
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input NETCLK_P, NETCLK_N,
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output gige_refclk_buf,
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input MGT156MHZ_CLK1_P, MGT156MHZ_CLK1_N,
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output xgige_refclk_buf,
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// Measurement Clock Generation
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input misc_clks_ref,
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output meas_clk,
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output ddr3_dma_clk,
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input misc_clks_reset,
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output reg misc_clks_locked,
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// CE Clock
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input clk200,
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output ce_clk,
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// PPS Capture & Selection
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input ext_pps_from_pin,
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input gps_pps_from_pin,
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input [3:0] pps_select,
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output reg pps_refclk
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);
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// Clock Buffering and Generation : ///////////////////////////////////////////////////
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//
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// Manually instantiate input buffers on all clocks, and a global buffer on the
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// Reference Clock for use in the rest of the design. All other clocks must have
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// global buffers other places, since the declarations here are for SI purposes.
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//
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///////////////////////////////////////////////////////////////////////////////////////
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wire ref_clk_buf;
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// FPGA Reference Clock Buffering
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//
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// Only require an IBUF and BUFG here, since an MMCM is (thankfully) not needed
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// to meet timing with the PPS signal.
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IBUFGDS ref_clk_ibuf (
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.O(ref_clk_buf),
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.I(FPGA_REFCLK_P),
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.IB(FPGA_REFCLK_N)
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);
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// BUFG ref_clk_bufg (
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// .I(ref_clk_buf),
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// .O(ref_clk)
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// );
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WrapBufg #(
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.kEnableIsAsync(1'b1)
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) ref_clk_bufg (
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.ClkIn(ref_clk_buf),
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.aCe(enable_ref_clk_async),
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.ClkOut(ref_clk)
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);
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// Buffers for SI Purposes
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//
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// Instantiate buffers on each of these differential clock inputs with DONT_TOUCH
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// attributes in order to preserve the internal termination regardless of whether
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// these clocks are used in the design. The lack of termination would place the
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// voltage swings for these pins outside the acceptable range for the FPGA inputs.
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(* dont_touch = "true" *) IBUFGDS wr_refclk_ibuf (
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.I (WB_20MHz_P),
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.IB(WB_20MHz_N),
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.O (wr_refclk_buf)
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);
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(* dont_touch = "true" *) IBUFGDS netclk_ref_ibuf (
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.I (NETCLK_REF_P),
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.IB(NETCLK_REF_N),
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.O (netclk_buf)
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);
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// Same deal for the MGT reference clock buffers.
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(* dont_touch = "true" *) IBUFDS_GTE2 gige_refclk_ibuf (
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.ODIV2(),
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.CEB (1'b0),
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.I (NETCLK_P),
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.IB(NETCLK_N),
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.O (gige_refclk_buf)
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);
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(* dont_touch = "true" *) IBUFDS_GTE2 ten_gige_refclk_ibuf (
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.ODIV2(),
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.CEB (1'b0),
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.I (MGT156MHZ_CLK1_P),
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.IB(MGT156MHZ_CLK1_N),
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.O (xgige_refclk_buf)
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);
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// Measurement Clock MMCM Instantiation
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//
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// This must be an MMCM to hit the weird rates we need for meas_clk. It takes the
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// 166.6667 MHz clock from the PS and provides the correct meas_clk rate for the TDC.
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// BUFG is embedded in the MMCM files.
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//----------------------------------------------------------------------------
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// Output Output Phase Duty Cycle Pk-to-Pk Phase
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// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
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//----------------------------------------------------------------------------
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// meas_clk___198.413______0.000______50.0______113.755____141.292
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// ddr3_dma_clk___303.819______0.000______50.0______105.705____141.292
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//
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//----------------------------------------------------------------------------
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// Input Clock Freq (MHz) Input Jitter (UI)
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//----------------------------------------------------------------------------
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// __primary________166.666667____________0.010
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wire misc_locked;
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misc_clock_gen misc_clock_gen_i (
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.clk_in (misc_clks_ref),
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.meas_clk (meas_clk),
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.ddr3_dma_clk (ddr3_dma_clk),
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.reset (misc_clks_reset),
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.locked (misc_locked)
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);
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// Compute Engine Clock
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//
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//----------------------------------------------------------------------------
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// Output Output Phase Duty Cycle Pk-to-Pk Phase
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// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
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//----------------------------------------------------------------------------
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// __ce_clk__266.66667______0.000______50.0______112.125____110.663
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//
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//----------------------------------------------------------------------------
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// Input Clock Freq (MHz) Input Jitter (UI)
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//----------------------------------------------------------------------------
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// __primary_____________200____________0.010
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wire ce_gen_clkfbout;
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wire ce_gen_clkout0;
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wire ce_gen_locked;
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PLLE2_ADV #(
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.BANDWIDTH ("OPTIMIZED"),
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.COMPENSATION ("ZHOLD" ),
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.STARTUP_WAIT ("FALSE" ),
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.DIVCLK_DIVIDE (3 ),
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.CLKFBOUT_MULT (16 ),
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.CLKFBOUT_PHASE (0.000 ),
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.CLKOUT0_DIVIDE (4 ),
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.CLKOUT0_PHASE (0.000 ),
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.CLKOUT0_DUTY_CYCLE(0.500 ),
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.CLKIN1_PERIOD (5.000 )
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) ce_clk_gen_i (
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.CLKFBOUT(ce_gen_clkfbout),
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.CLKOUT0 (ce_gen_clkout0 ),
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.CLKOUT1 ( ),
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.CLKOUT2 ( ),
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.CLKOUT3 ( ),
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.CLKOUT4 ( ),
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.CLKOUT5 ( ),
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.CLKFBIN (ce_gen_clkfbout),
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.CLKIN1 (clk200 ),
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.CLKIN2 (1'b0 ),
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.CLKINSEL(1'b1 ),
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.DADDR (7'h0 ),
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.DCLK (1'b0 ),
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.DEN (1'b0 ),
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.DI (16'h0 ),
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.DO ( ),
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.DRDY ( ),
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.DWE (1'b0 ),
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.LOCKED (ce_gen_locked ),
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.PWRDWN (1'b0 ),
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.RST (misc_clks_reset)
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);
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BUFG ce_clk_buf (
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.O(ce_clk ),
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.I(ce_gen_clkout0)
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);
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wire misc_locked_clk200;
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wire ce_lockec_clk200;
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synchronizer synchronizer_misc (
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.clk(clk200 ),
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.rst(1'b0 ),
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.in (misc_locked ),
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.out(misc_locked_clk200)
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);
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synchronizer synchronizer_ce (
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.clk(clk200 ),
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.rst(1'b0 ),
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.in (ce_gen_locked ),
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.out(ce_locked_clk200)
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);
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always @(posedge clk200) begin
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misc_clks_locked <= misc_locked_clk200 & ce_locked_clk200;
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end
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// PPS Capture and Generation : ///////////////////////////////////////////////////////
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//
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// The following shows the support matrix for PPS with respect to the
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// reference clock source and rate.
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// _______________________________
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// ____________| PPS |
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// | Clocks | External | FPGA | GPSDO | WR |
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// |--------------------------------------------|
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// |External 10 | x | x | (x) | |
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// |Internal 25 | | x | | x |
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// |GPSDO 20 | | | x | |
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// |--------------------------------------------|
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//
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// A note on external clock + GPSDO timing: The hardware doesn't prohibit this
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// use case, but GPSDO and external clock are guaranteed to be not matched, so
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// this will certainly cause a non-deterministic time alignment between devices.
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// Using this combination will still allow receiving samples, but there is no
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// guarantee regarding phase/time alignment whatsoever.
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//
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///////////////////////////////////////////////////////////////////////////////////////
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wire pps_ext_refclk;
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wire pps_gps_refclk;
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wire [3:0] pps_select_refclk;
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// Generate two internal PPS signals, each with a 25% duty cycle, based on
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// 10 MHz and 25 MHz Reference Clock rates. Only one will be used at a time.
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wire int_pps_10mhz_refclk;
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pps_generator #(
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.CLK_FREQ(32'd10_000_000), .DUTY_CYCLE(25)
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) pps_gen_10 (
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.clk(ref_clk), .reset(1'b0), .pps(int_pps_10mhz_refclk)
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);
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wire int_pps_25mhz_refclk;
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pps_generator #(
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.CLK_FREQ(32'd25_000_000), .DUTY_CYCLE(25)
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) pps_gen_25 (
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.clk(ref_clk), .reset(1'b0), .pps(int_pps_25mhz_refclk)
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);
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// Capture the external PPSs with a FF before sending them to the mux. To be safe,
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// we double-synchronize the external signals. If we meet timing (which we should)
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// then this is a two-cycle delay. If we don't meet timing, then it's 1-2 cycles
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// and our system timing is thrown off--but at least our downstream logic doesn't
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// go metastable!
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synchronizer #(
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.FALSE_PATH_TO_IN(0)
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) ext_pps_dsync (
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.clk(ref_clk), .rst(1'b0), .in(ext_pps_from_pin), .out(pps_ext_refclk)
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);
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// Same deal with the GPSDO PPS input. Double-sync, then use it.
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synchronizer #(
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.FALSE_PATH_TO_IN(0)
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) gps_pps_dsync (
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.clk(ref_clk), .rst(1'b0), .in(gps_pps_from_pin), .out(pps_gps_refclk)
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);
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// Synchronize the select bits over to the reference clock as well. Note that this is
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// a vector, so we could have some non-one-hot values creep through when changing.
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// See the note below as to why this is safe.
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synchronizer #(
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.FALSE_PATH_TO_IN(1),
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.WIDTH(4)
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) pps_select_dsync (
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.clk(ref_clk), .rst(1'b0), .in(pps_select), .out(pps_select_refclk)
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);
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// Bit locations for the pps_select vector.
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localparam BIT_PPS_SEL_INT_10 = 0;
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localparam BIT_PPS_SEL_INT_25 = 1;
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localparam BIT_PPS_SEL_EXT = 2;
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localparam BIT_PPS_SEL_GPSDO = 3;
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// PPS MUX - selects internal or external PPS.
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always @(posedge ref_clk) begin
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// Encoding is one-hot on these bits. It is possible when the vector is being double-
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// synchronized to the reference clock domain that there could be multiple bits
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// asserted simultaneously. This is not problematic because the order of operations
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// in the following selection mux should take over and only one PPS should win.
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// This could result in glitches, but that is expected during ANY PPS switchover
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// since the switch is performed asynchronously to the PPS signal.
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if (pps_select_refclk[BIT_PPS_SEL_INT_10])
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pps_refclk <= int_pps_10mhz_refclk;
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else if (pps_select_refclk[BIT_PPS_SEL_INT_25])
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pps_refclk <= int_pps_25mhz_refclk;
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else if (pps_select_refclk[BIT_PPS_SEL_EXT])
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pps_refclk <= pps_ext_refclk;
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else if (pps_select_refclk[BIT_PPS_SEL_GPSDO])
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pps_refclk <= pps_gps_refclk;
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else
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pps_refclk <= pps_ext_refclk; // Compatibility with old SW stacks, pps_select_refclk = 0 = external
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end
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endmodule
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