miegl/b210-k7-fpga
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b210-k7-fpga/top/e31x
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Wade Fife b8ded164e5 fpga: rfnoc: Remove rfnoc_version from target YAML 
This causes the latest RFNoC protocol version to be used by default
and avoids the need to update YAML files every time the RFNoC
protocol version gets bumped.


Original-commit: 92016a585a5223a9a7678134e318e412875b64c2
2022-05-11 12:29:35 -07:00
..
dts
e31x: Swap out liberio for internal Ethernet
2020-07-16 10:00:12 -05:00
ip
fpga: e31x: Fix DRAM traffic gen IP name
2022-03-23 08:55:36 -05:00
sim
fpga: e31x: Update DRAM IP simulation
2022-03-23 08:55:36 -05:00
.gitignore
fpga: e31x: Add gitignore file
2020-07-18 13:33:42 -05:00
axi_pmu.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_e31x.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_core.v
fpga: Use PROTOVER and CHDR_W from RFNoC image builder
2022-03-29 14:45:04 -05:00
e31x_dram.v
fpga: e31x: Add DRAM support
2022-02-10 18:13:44 -07:00
e31x_idle_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_idle.v
e31x: Swap out liberio for internal ethernet in the idle image
2020-07-18 11:52:58 -05:00
e31x_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_timing.xdc
fpga: e31x: Update constraints to avoid timing issues
2020-04-08 17:24:15 -05:00
e31x.v
fpga: Use PROTOVER and CHDR_W from RFNoC image builder
2022-03-29 14:45:04 -05:00
e310_io.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e310_rfnoc_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
e310_rfnoc_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
e310_rfnoc_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
e310_static_router.hex
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
Makefile
fpga: e31x: Add DRAM support
2022-02-10 18:13:44 -07:00
Makefile.e31x.inc
fpga: Use PROTOVER and CHDR_W from RFNoC image builder
2022-03-29 14:45:04 -05:00
ppsloop.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
setupenv.sh
fpga: Set default part for sim in setupenv.sh
2021-08-30 08:20:10 -05:00
spi_slave.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00