adf6f576c6
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
77 lines
3.3 KiB
Systemverilog
77 lines
3.3 KiB
Systemverilog
//
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// Copyright 2023 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: dio_regmap_utils.vh
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// Description:
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// The constants in this file are autogenerated by XmlParse.
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//===============================================================================
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// A numerically ordered list of registers and their HDL source files
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//===============================================================================
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// DIO_MASTER_REGISTER : 0x0 (x4xx_dio.v)
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// DIO_DIRECTION_REGISTER : 0x4 (x4xx_dio.v)
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// DIO_INPUT_REGISTER : 0x8 (x4xx_dio.v)
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// DIO_OUTPUT_REGISTER : 0xC (x4xx_dio.v)
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// DIO_SOURCE_REGISTER : 0x10 (x4xx_dio.v)
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// RADIO_SOURCE_REGISTER : 0x14 (x4xx_dio.v)
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// INTERFACE_DIO_SELECT : 0x18 (x4xx_dio.v)
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// DIO_OVERRIDE : 0x1C (x4xx_dio.v)
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// SW_DIO_CONTROL : 0x20 (x4xx_dio.v)
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//===============================================================================
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// RegTypes
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//===============================================================================
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// DIO_CONTROL_REG Type (from x4xx_dio.v)
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localparam DIO_CONTROL_REG_SIZE = 32;
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localparam DIO_CONTROL_REG_MASK = 32'hFFF0FFF;
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localparam DIO_PORT_A_SIZE = 12; //DIO_CONTROL_REG:DIO_PORT_A
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localparam DIO_PORT_A_MSB = 11; //DIO_CONTROL_REG:DIO_PORT_A
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localparam DIO_PORT_A = 0; //DIO_CONTROL_REG:DIO_PORT_A
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localparam DIO_PORT_B_SIZE = 12; //DIO_CONTROL_REG:DIO_PORT_B
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localparam DIO_PORT_B_MSB = 27; //DIO_CONTROL_REG:DIO_PORT_B
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localparam DIO_PORT_B = 16; //DIO_CONTROL_REG:DIO_PORT_B
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//===============================================================================
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// Register Group DIO_REGS
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//===============================================================================
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// DIO_MASTER_REGISTER Register (from x4xx_dio.v)
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localparam DIO_MASTER_REGISTER = 'h0; // Register Offset
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localparam DIO_MASTER_REGISTER_SIZE = 32; // register width in bits
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// DIO_DIRECTION_REGISTER Register (from x4xx_dio.v)
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localparam DIO_DIRECTION_REGISTER = 'h4; // Register Offset
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localparam DIO_DIRECTION_REGISTER_SIZE = 32; // register width in bits
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// DIO_INPUT_REGISTER Register (from x4xx_dio.v)
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localparam DIO_INPUT_REGISTER = 'h8; // Register Offset
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localparam DIO_INPUT_REGISTER_SIZE = 32; // register width in bits
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// DIO_OUTPUT_REGISTER Register (from x4xx_dio.v)
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localparam DIO_OUTPUT_REGISTER = 'hC; // Register Offset
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localparam DIO_OUTPUT_REGISTER_SIZE = 32; // register width in bits
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// DIO_SOURCE_REGISTER Register (from x4xx_dio.v)
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localparam DIO_SOURCE_REGISTER = 'h10; // Register Offset
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localparam DIO_SOURCE_REGISTER_SIZE = 32; // register width in bits
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// RADIO_SOURCE_REGISTER Register (from x4xx_dio.v)
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localparam RADIO_SOURCE_REGISTER = 'h14; // Register Offset
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localparam RADIO_SOURCE_REGISTER_SIZE = 32; // register width in bits
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// INTERFACE_DIO_SELECT Register (from x4xx_dio.v)
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localparam INTERFACE_DIO_SELECT = 'h18; // Register Offset
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localparam INTERFACE_DIO_SELECT_SIZE = 32; // register width in bits
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// DIO_OVERRIDE Register (from x4xx_dio.v)
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localparam DIO_OVERRIDE = 'h1C; // Register Offset
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localparam DIO_OVERRIDE_SIZE = 32; // register width in bits
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// SW_DIO_CONTROL Register (from x4xx_dio.v)
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localparam SW_DIO_CONTROL = 'h20; // Register Offset
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localparam SW_DIO_CONTROL_SIZE = 32; // register width in bits
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