223 lines
6.7 KiB
Verilog
223 lines
6.7 KiB
Verilog
//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: led_control
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//
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// Description:
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// Implements control over LED state via CtrlPort. The default state
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// has the LEDs disabled.
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//
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`default_nettype none
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module led_control #(
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parameter BASE_ADDRESS = 0,
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parameter REGMAP_SIZE = 8'h1
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) (
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// Clock and reset
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Request
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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// Response
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output reg s_ctrlport_resp_ack,
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output reg [ 1:0] s_ctrlport_resp_status,
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output reg [31:0] s_ctrlport_resp_data,
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// LED Control (domain: ctrlport_clk)
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output reg ch0_rx2_led,
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output reg ch0_tx_led,
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output reg ch0_rx_led,
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output reg ch1_rx2_led,
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output reg ch1_tx_led,
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output reg ch1_rx_led,
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output reg ch2_rx2_led,
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output reg ch2_tx_led,
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output reg ch2_rx_led,
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output reg ch3_rx2_led,
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output reg ch3_tx_led,
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output reg ch3_rx_led
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);
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`include "../regmap/x440/led_setup_regmap_utils.vh"
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`include "../../../../lib/rfnoc/core/ctrlport.vh"
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//---------------------------------------------------------------
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// ATR memory signals
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//---------------------------------------------------------------
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reg [31:0] led_ctrl_reg = 32'h0;
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//---------------------------------------------------------------
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// Handling of CtrlPort
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//---------------------------------------------------------------
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// Check of request address is targeted for this module.
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wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + REGMAP_SIZE);
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always @(posedge ctrlport_clk) begin
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// reset internal registers and responses
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if (ctrlport_rst) begin
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s_ctrlport_resp_ack <= 1'b0;
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s_ctrlport_resp_status <= 2'b0;
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s_ctrlport_resp_data <= 32'b0;
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end else begin
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// write requests
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if (s_ctrlport_req_wr) begin
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// always issue an ack and no data
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_data <= {32{1'bx}};
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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case (s_ctrlport_req_addr)
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BASE_ADDRESS + LED_CONTROL: begin
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led_ctrl_reg <= s_ctrlport_req_data;
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end
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// error on undefined address
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default: begin
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// no response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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//req_rd not delayed
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end else if (s_ctrlport_req_rd) begin
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// default assumption: valid request
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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s_ctrlport_resp_data <= {32{1'b0}};
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case (s_ctrlport_req_addr)
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BASE_ADDRESS : begin
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s_ctrlport_resp_data <= led_ctrl_reg & LED_CONTROL_MASK;
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end
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// error on undefined address
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default: begin
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// no response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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// no request
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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end
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always @(posedge ctrlport_clk) begin
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//outputs
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ch0_rx2_led <= led_ctrl_reg[CH0_RX2_LED_EN];
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ch0_tx_led <= led_ctrl_reg[CH0_TRX1_LED_RED_EN];
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ch0_rx_led <= led_ctrl_reg[CH0_TRX1_LED_GR_EN];
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ch1_rx2_led <= led_ctrl_reg[CH1_RX2_LED_EN];
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ch1_tx_led <= led_ctrl_reg[CH1_TRX1_LED_RED_EN];
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ch1_rx_led <= led_ctrl_reg[CH1_TRX1_LED_GR_EN];
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ch2_rx2_led <= led_ctrl_reg[CH2_RX2_LED_EN];
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ch2_tx_led <= led_ctrl_reg[CH2_TRX1_LED_RED_EN];
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ch2_rx_led <= led_ctrl_reg[CH2_TRX1_LED_GR_EN];
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ch3_rx2_led <= led_ctrl_reg[CH3_RX2_LED_EN];
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ch3_tx_led <= led_ctrl_reg[CH3_TRX1_LED_RED_EN];
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ch3_rx_led <= led_ctrl_reg[CH3_TRX1_LED_GR_EN];
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end
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endmodule
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`default_nettype wire
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//XmlParse xml_on
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//<regmap name="LED_SETUP_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
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// <group name="LED_SETUP_REGISTERS">
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// <info>
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// Contains registers that control the LEDs.
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// </info>
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// <register name="LED_CONTROL" size="32" offset="0x0" attributes="Readable|Writable">
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// <info>
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// This register configures RF Frontend LEDs.
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// </info>
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// <bitfield name="CH0_RX2_LED_EN" range="0" initialvalue="0">
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// <info>
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// Enables the Ch0 Rx2 Green LED
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// </info>
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// </bitfield>
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// <bitfield name="CH0_TRX1_LED_RED_EN" range="1" initialvalue="0">
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// <info>
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// Enables the Ch0 TRX (TX) Red LED
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// </info>
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// </bitfield>
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// <bitfield name="CH0_TRX1_LED_GR_EN" range="2" initialvalue="0">
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// <info>
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// Enables the Ch0 TRX (RX) Green LED
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// </info>
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// </bitfield>
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// <bitfield name="CH1_RX2_LED_EN" range="8" initialvalue="0">
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// <info>
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// Enables the Ch1 Rx2 Green LED
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// </info>
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// </bitfield>
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// <bitfield name="CH1_TRX1_LED_RED_EN" range="9" initialvalue="0">
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// <info>
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// Enables the Ch1 TRX (TX) Red LED
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// </info>
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// </bitfield>
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// <bitfield name="CH1_TRX1_LED_GR_EN" range="10" initialvalue="0">
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// <info>
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// Enables the Ch1 TRX (RX) Green LED
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// </info>
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// </bitfield>
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// <bitfield name="CH2_RX2_LED_EN" range="16" initialvalue="0">
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// <info>
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// Enables the Ch2 Rx2 Green LED
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// </info>
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// </bitfield>
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// <bitfield name="CH2_TRX1_LED_RED_EN" range="17" initialvalue="0">
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// <info>
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// Enables the Ch2 TRX (TX) Red LED
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// </info>
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// </bitfield>
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// <bitfield name="CH2_TRX1_LED_GR_EN" range="18" initialvalue="0">
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// <info>
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// Enables the Ch2 TRX (RX) Green LED
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// </info>
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// </bitfield>
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// <bitfield name="CH3_RX2_LED_EN" range="24" initialvalue="0">
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// <info>
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// Enables the Ch3 Rx2 Green LED
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// </info>
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// </bitfield>
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// <bitfield name="CH3_TRX1_LED_RED_EN" range="25" initialvalue="0">
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// <info>
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// Enables the Ch3 TRX (TX) Red LED
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// </info>
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// </bitfield>
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// <bitfield name="CH3_TRX1_LED_GR_EN" range="26" initialvalue="0">
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// <info>
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// Enables the Ch3 TRX (RX) Green LED
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// </info>
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// </bitfield>
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// </register>
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// </group>
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//</regmap>
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//XmlParse xml_off
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