42 lines
1.3 KiB
Makefile
42 lines
1.3 KiB
Makefile
#
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# Copyright 2015 Ettus Research LLC
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../..)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Define part using PART_ID (<device>/<package>/<speedgrade>)
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ARCH = zynq
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PART_ID= xc7z020/clg484/-1
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DESIGN_SRCS = $(abspath ../../e310_io.v) \
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$(abspath $(addprefix $(BASE_DIR)/../lib/control/, \
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synchronizer.v \
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synchronizer_impl.v))
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define toplevel module
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SIM_TOP = e310_io_tb glbl
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SIM_SRCS = \
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$(abspath e310_io_tb.sv) \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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