116 lines
4.6 KiB
Systemverilog
116 lines
4.6 KiB
Systemverilog
//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_clk_cross
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//
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// Description:
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//
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// Crosses a CTRL Port request and response between two clock domains.
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//
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module ctrlport_clk_cross
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import ctrlport_pkg::*;
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(
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input logic rst, // Can be either clock domain, but must be glitch-free
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//---------------------------------------------------------------------------
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// Input Clock Domain (Slave Interface)
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//---------------------------------------------------------------------------
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input logic s_ctrlport_clk,
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input logic s_ctrlport_req_wr,
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input logic s_ctrlport_req_rd,
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input logic [ CTRLPORT_ADDR_W-1:0] s_ctrlport_req_addr,
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input logic [ CTRLPORT_PORTID_W-1:0] s_ctrlport_req_portid,
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input logic [CTRLPORT_REM_EPID_W-1:0] s_ctrlport_req_rem_epid,
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input logic [ CTRLPORT_PORTID_W-1:0] s_ctrlport_req_rem_portid,
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input logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_req_data,
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input logic [ CTRLPORT_BYTE_EN_W-1:0] s_ctrlport_req_byte_en,
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input logic s_ctrlport_req_has_time,
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input logic [ CTRLPORT_TIME_W-1:0] s_ctrlport_req_time,
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output logic s_ctrlport_resp_ack,
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output logic [ CTRLPORT_STS_W-1:0] s_ctrlport_resp_status,
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output logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_resp_data,
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//---------------------------------------------------------------------------
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// Output Clock Domain (Master Interface)
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//---------------------------------------------------------------------------
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input logic m_ctrlport_clk,
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output logic m_ctrlport_req_wr,
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output logic m_ctrlport_req_rd,
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output logic [ CTRLPORT_ADDR_W-1:0] m_ctrlport_req_addr,
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output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_portid,
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output logic [CTRLPORT_REM_EPID_W-1:0] m_ctrlport_req_rem_epid,
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output logic [ CTRLPORT_PORTID_W-1:0] m_ctrlport_req_rem_portid,
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output logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_req_data,
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output logic [ CTRLPORT_BYTE_EN_W-1:0] m_ctrlport_req_byte_en,
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output logic m_ctrlport_req_has_time,
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output logic [ CTRLPORT_TIME_W-1:0] m_ctrlport_req_time,
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input logic m_ctrlport_resp_ack,
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input logic [ CTRLPORT_STS_W-1:0] m_ctrlport_resp_status,
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input logic [ CTRLPORT_DATA_W-1:0] m_ctrlport_resp_data
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);
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import ctrlport_pkg::*;
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// Reset sync to both clock domains
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logic m_rst, s_rst;
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reset_sync slave_reset_sync_inst (
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.clk(s_ctrlport_clk), .reset_in(rst), .reset_out(s_rst)
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);
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reset_sync master_reset_sync_inst (
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.clk(m_ctrlport_clk), .reset_in(rst), .reset_out(m_rst)
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);
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// Define interfaces
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ctrlport_if s_ctrlport_if(.clk(s_ctrlport_clk), .rst(s_rst));
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ctrlport_if m_ctrlport_if(.clk(m_ctrlport_clk), .rst(m_rst));
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// Map existing ports to ctrlport_if
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always_comb begin
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s_ctrlport_if.req.wr = s_ctrlport_req_wr;
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s_ctrlport_if.req.rd = s_ctrlport_req_rd;
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s_ctrlport_if.req.addr = s_ctrlport_req_addr;
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s_ctrlport_if.req.port_id = s_ctrlport_req_portid;
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s_ctrlport_if.req.remote_epid = s_ctrlport_req_rem_epid;
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s_ctrlport_if.req.remote_portid = s_ctrlport_req_rem_portid;
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s_ctrlport_if.req.data = s_ctrlport_req_data;
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s_ctrlport_if.req.byte_en = s_ctrlport_req_byte_en;
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s_ctrlport_if.req.has_time = s_ctrlport_req_has_time;
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s_ctrlport_if.req.timestamp = s_ctrlport_req_time;
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s_ctrlport_resp_ack = s_ctrlport_if.resp.ack;
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s_ctrlport_resp_status = s_ctrlport_if.resp.status;
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s_ctrlport_resp_data = s_ctrlport_if.resp.data;
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end
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// Instantiate ctrlport_if_clk_cross module
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ctrlport_if_clk_cross clk_cross_inst (
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.s_ctrlport(s_ctrlport_if),
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.m_ctrlport(m_ctrlport_if)
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);
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// Unpack ctrlport_if to output port
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always_comb begin
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m_ctrlport_req_wr = m_ctrlport_if.req.wr;
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m_ctrlport_req_rd = m_ctrlport_if.req.rd;
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m_ctrlport_req_addr = m_ctrlport_if.req.addr;
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m_ctrlport_req_portid = m_ctrlport_if.req.port_id;
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m_ctrlport_req_rem_epid = m_ctrlport_if.req.remote_epid;
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m_ctrlport_req_rem_portid = m_ctrlport_if.req.remote_portid;
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m_ctrlport_req_data = m_ctrlport_if.req.data;
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m_ctrlport_req_byte_en = m_ctrlport_if.req.byte_en;
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m_ctrlport_req_has_time = m_ctrlport_if.req.has_time;
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m_ctrlport_req_time = m_ctrlport_if.req.timestamp;
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m_ctrlport_if.resp.ack = m_ctrlport_resp_ack;
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m_ctrlport_if.resp.status = ctrlport_status_t'(m_ctrlport_resp_status);
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m_ctrlport_if.resp.data = m_ctrlport_resp_data;
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end
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endmodule
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