303 lines
12 KiB
Systemverilog
303 lines
12 KiB
Systemverilog
//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axis_load_merge
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//
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// Description:
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//
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// Takes in multiple AXI4-Stream interfaces and merges the contents into a
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// single stream, packet by packet. The packets will be merged sequentially,
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// first accepting a packet from port 0, then from port 1, and so on, in a
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// circular manner. The module will wait for the packet to arrive on the
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// expected port before moving onto the next port.
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//
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// This module matches the behavior of axis_load_split, such that the results
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// from multiple processing instances can be merged back together in the same
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// order they were received by the axis_load_split module.
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//
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// The handling of TUSER deserves some explanation. If the input-port width
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// is the same as the output-port width, then the TUSER input is passed
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// through along with the corresponding TDATA like normal. But, if the
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// output-word size is larger than the input-word size, then there are
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// multiple N TUSER inputs for each TUSER output. The USER_SEL parameter
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// selects which one will be output. It can be in the range [0,N-1], where 0
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// selects the first of the N TUSER inputs for the next TUSER output and N-1
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// selects the last of the N TUSER inputs.
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//
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// Parameters:
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//
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// IN_DATA_W : Width of TDATA in bits for the input port.
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// IN_FIFO_SIZE : Log base-2 of the input FIFO size, in units of
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// IN_DATA_W-sized words. Typically, this would be large
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// enough to buffer one entire packet. Set to -1 to remove.
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// IN_NUM_PORTS : The number of input streams across which to distribute
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// the packets.
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// OUT_DATA_W : Width of TDATA in bits for the output port.
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// OUT_FIFO_SIZE : Log base-2 of the output FIFO size, in units of
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// OUT_DATA_W-sized words. Set to -1 to remove, 1 to add a
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// register that cuts timing paths, or whichever size you
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// desire.
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// USER_W : Width of TUSER in bits for both input and output ports.
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// USER_SEL : When the output word size is a multiple of the input word
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// size, USER_SEL indicates which TUSER input value will be
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// passed along with each TDATA output value. A value of 0
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// indicates that the first TUSER value that was input for a
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// corresponding output word will be used for that output
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// word. It can be in the range from 0 up to the number of
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// output words per input words.
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//
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`default_nettype none
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module axis_load_merge #(
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int IN_DATA_W = 32,
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int IN_FIFO_SIZE = 10,
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int IN_NUM_PORTS = 2,
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int OUT_DATA_W = 64,
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int OUT_FIFO_SIZE = 1,
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int USER_W = 1,
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int USER_SEL = 0
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) (
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input wire clk,
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input wire rst,
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// Input streams
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input wire [IN_DATA_W-1:0] i_tdata [IN_NUM_PORTS],
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input wire [ USER_W-1:0] i_tuser [IN_NUM_PORTS],
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input wire i_tlast [IN_NUM_PORTS],
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input wire i_tvalid [IN_NUM_PORTS],
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output logic i_tready [IN_NUM_PORTS],
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// Single output stream
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output logic [OUT_DATA_W-1:0] o_tdata,
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output logic [ USER_W-1:0] o_tuser,
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output logic o_tlast,
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output logic o_tvalid,
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input wire o_tready
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);
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// Elaboration-time assertions
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if (IN_DATA_W > OUT_DATA_W) begin : check_size
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$error("IN_DATA_W must not exceed OUT_DATA_W");
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end
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if (OUT_DATA_W % IN_DATA_W != 0) begin : check_multiple
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$error("OUT_DATA_W must be a multiple of IN_DATA_W");
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end
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//-------------------------------------------------------------------------
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// Resize
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//-------------------------------------------------------------------------
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logic [OUT_DATA_W-1:0] resize_tdata [IN_NUM_PORTS];
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logic [ USER_W-1:0] resize_tuser [IN_NUM_PORTS];
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logic resize_tlast [IN_NUM_PORTS];
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logic resize_tvalid [IN_NUM_PORTS];
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logic resize_tready [IN_NUM_PORTS];
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if (IN_DATA_W == OUT_DATA_W) begin : gen_no_resize
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assign resize_tdata = i_tdata;
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assign resize_tuser = i_tuser;
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assign resize_tlast = i_tlast;
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assign resize_tvalid = i_tvalid;
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assign i_tready = resize_tready;
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end else begin : gen_resize
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for (genvar idx = 0; idx < IN_NUM_PORTS; idx++) begin : gen_axis_width_conv
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localparam int OUT_WORDS = OUT_DATA_W/IN_DATA_W;
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localparam int COUNT_W = $clog2(OUT_WORDS);
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if (USER_SEL < 0 || USER_SEL >= OUT_WORDS) begin : check_parameters
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$error("USER_SEL is outside of allowed range");
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end
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//-----------------------------------------
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// Data Width Conversion
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//-----------------------------------------
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axis_width_conv #(
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.WORD_W (IN_DATA_W),
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.IN_WORDS (1 ),
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.OUT_WORDS(OUT_WORDS),
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.SYNC_CLKS(1 ),
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.PIPELINE ("INOUT" )
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) axis_width_conv_i (
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.s_axis_aclk (clk ),
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.s_axis_rst (rst ),
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.s_axis_tdata (i_tdata[idx] ),
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.s_axis_tkeep ('1 ),
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.s_axis_tlast (i_tlast[idx] ),
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.s_axis_tvalid(i_tvalid[idx] ),
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.s_axis_tready(i_tready[idx] ),
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.m_axis_aclk (clk ),
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.m_axis_rst (rst ),
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.m_axis_tdata (resize_tdata[idx] ),
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.m_axis_tkeep ( ),
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.m_axis_tlast (resize_tlast[idx] ),
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.m_axis_tvalid(resize_tvalid[idx]),
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.m_axis_tready(resize_tready[idx])
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);
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//-----------------------------------------
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// TUSER Handling
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//-----------------------------------------
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// We write to the TUSER FIFO at a rate of 1/OUT_WORDS, but read from
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// the TUSER FIFO in lock-step with the output of axis_width_conv
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// module. The USER_SEL parameter selects which TUSER gets input.
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logic user_fifo_i_tvalid;
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logic user_fifo_i_tready;
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logic user_fifo_o_tvalid;
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logic [COUNT_W-1:0] word_count = '0;
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// This counter tells when we're inputting the selected TUSER for the
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// current output word, so we know when to write it to the FIFO. The
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// counter is initialized such that it will assert after the first
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// USER_SEL cycles, then repeats every OUT_WORDS cycles after that.
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always_ff @(posedge clk) begin
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if (i_tvalid[idx] && i_tready[idx]) begin
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if (word_count == OUT_WORDS-1) begin
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word_count <= '0;
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end else begin
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word_count <= word_count + 1;
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end
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end
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if (rst) begin
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word_count <= '0;
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end
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end
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assign user_fifo_i_tvalid = (word_count == USER_SEL) && i_tvalid[idx] && i_tready[idx];
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axi_fifo #(
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.WIDTH(USER_W),
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.SIZE (2 )
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) axi_fifo_tuser (
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.clk (clk ),
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.reset (rst ),
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.clear ('0 ),
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.i_tdata (i_tuser[idx] ),
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.i_tvalid(user_fifo_i_tvalid ),
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.i_tready(user_fifo_i_tready ),
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.o_tdata (resize_tuser[idx] ),
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.o_tvalid(user_fifo_o_tvalid ),
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.o_tready(resize_tvalid[idx] && resize_tready[idx]),
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.occupied( ),
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.space ( )
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);
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// Make sure we don't overflow/underflow the TUSER FIFO
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//synthesis translate_off
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always_ff @(posedge clk) begin
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if (user_fifo_i_tvalid && !user_fifo_i_tready) begin
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$error("TUSER FIFO overflow");
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end
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if (resize_tvalid[idx] && resize_tready[idx] && !user_fifo_o_tvalid) begin
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$error("TUSER FIFO underflow");
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end
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end
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//synthesis translate_on
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end
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end
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//---------------------------------------------------------------------------
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// Input FIFOs
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//---------------------------------------------------------------------------
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logic [OUT_DATA_W-1:0] fifo_tdata [IN_NUM_PORTS];
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logic [ USER_W-1:0] fifo_tuser [IN_NUM_PORTS];
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logic fifo_tlast [IN_NUM_PORTS];
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logic fifo_tvalid [IN_NUM_PORTS];
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logic fifo_tready [IN_NUM_PORTS];
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for (genvar idx = 0; idx < IN_NUM_PORTS; idx++) begin : gen_axi_fifos
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axi_fifo #(
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.WIDTH(1 + USER_W + OUT_DATA_W ),
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.SIZE (IN_FIFO_SIZE - $clog2(OUT_DATA_W/IN_DATA_W))
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) axi_fifo_in (
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.clk (clk ),
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.reset (rst ),
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.clear (1'b0 ),
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.i_tdata ({resize_tlast[idx], resize_tuser[idx], resize_tdata[idx]}),
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.i_tvalid(resize_tvalid[idx] ),
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.i_tready(resize_tready[idx] ),
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.o_tdata ({fifo_tlast[idx], fifo_tuser[idx], fifo_tdata[idx]} ),
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.o_tvalid(fifo_tvalid[idx] ),
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.o_tready(fifo_tready[idx] ),
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.space ( ),
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.occupied( )
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);
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end
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//---------------------------------------------------------------------------
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// Merge Logic
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//---------------------------------------------------------------------------
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logic [OUT_DATA_W-1:0] merge_tdata;
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logic [ USER_W-1:0] merge_tuser;
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logic merge_tlast;
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logic merge_tvalid;
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logic merge_tready;
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// Currently selected port
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logic [$clog2(IN_NUM_PORTS)-1:0] st_port;
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// Merge state machine. Tracks and advances the currently selected port.
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always_ff @(posedge clk) begin
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if (rst) begin
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st_port <= '0;
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end else begin
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if (merge_tvalid && merge_tready && merge_tlast) begin
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if (st_port == IN_NUM_PORTS-1) begin
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st_port <= '0;
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end else begin
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st_port <= st_port + 1;
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end
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end
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end
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end
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// Connect the selected input to the output
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assign merge_tdata = fifo_tdata[st_port];
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assign merge_tuser = fifo_tuser[st_port];
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assign merge_tlast = fifo_tlast[st_port];
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assign merge_tvalid = fifo_tvalid[st_port];
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for (genvar idx = 0; idx < IN_NUM_PORTS; idx++) begin : gen_merge
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assign fifo_tready[idx] = merge_tready && (st_port == idx);
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end
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//---------------------------------------------------------------------------
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// Output FIFOs
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//---------------------------------------------------------------------------
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axi_fifo #(
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.WIDTH(1 + USER_W + OUT_DATA_W),
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.SIZE (OUT_FIFO_SIZE )
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) axi_fifo_out (
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.clk (clk ),
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.reset (rst ),
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.clear (1'b0 ),
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.i_tdata ({merge_tlast, merge_tuser, merge_tdata}),
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.i_tvalid(merge_tvalid ),
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.i_tready(merge_tready ),
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.o_tdata ({o_tlast, o_tuser, o_tdata} ),
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.o_tvalid(o_tvalid ),
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.o_tready(o_tready ),
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.space ( ),
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.occupied( )
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);
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endmodule : axis_load_merge
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`default_nettype wire
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