134 lines
4.3 KiB
VHDL
134 lines
4.3 KiB
VHDL
--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: tb_duc_400m_saturate
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--
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-- Description:
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--
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-- Self-checking testbench used to check the saturation logic needed in DDC.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library WORK;
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use WORK.PkgRf.all;
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entity tb_duc_400m_saturate is
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end tb_duc_400m_saturate;
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architecture RTL of tb_duc_400m_saturate is
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component duc_400m_saturate
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port (
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Clk : in std_logic;
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cDataIn : in std_logic_vector(287 downto 0);
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cDataValidIn : in std_logic;
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cReadyForInput : out std_logic;
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cDataOut : out std_logic_vector(191 downto 0);
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cDataValidOut : out std_logic := '0');
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end component;
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signal TestStart : boolean := false;
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signal cDataIn : std_logic_vector(287 downto 0);
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signal cDataOut : std_logic_vector(191 downto 0);
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signal cDataValidIn : std_logic;
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signal cDataValidOut : std_logic;
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signal StopSim : boolean;
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constant kPer : time := 10 ns;
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constant kSamplesPerClock : integer := 12;
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signal Clk: std_logic := '1';
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procedure ClkWait(X : positive := 1) is
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begin
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for i in 1 to X loop
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wait until rising_edge(Clk);
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end loop;
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end procedure ClkWait;
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begin
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Clk <= not Clk after kPer/2 when not StopSim else '0';
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-- cReadyForInput is a constant in the design and is not being tested.
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dut: duc_400m_saturate
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port map (
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Clk => Clk,
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cDataIn => cDataIn,
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cDataValidIn => cDataValidIn,
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cReadyForInput => open,
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cDataOut => cDataOut,
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cDataValidOut => cDataValidOut);
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main: process
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begin
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ClkWait;
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TestStart <= false;
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ClkWait;
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TestStart <= true;
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-- This wait is needed to sweep through the entire range of 18 bits signed
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-- value. Since we operate the saturation logic with 12 samples per cycle,
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-- we need to wait for 2^kDucDataOutWidth/12. We are adding an extra 10
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-- clock cycles wait just as a buffer for the DUT latency.
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ClkWait(2**kDucDataOutWidth/kSamplesPerClock + 10);
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StopSim <= true;
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wait;
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end process;
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-- Process to generate 18-bit signed data.
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DataGen: process(Clk)
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variable Sample : Sample18_t := kSmallest18;
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begin
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if falling_edge(Clk) then
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if TestStart then
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cDataValidIn <= '1';
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cDataIn <= "000000" & std_logic_vector(Sample+kSamplesPerClock-1) &
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"000000" & std_logic_vector(Sample+kSamplesPerClock-2) &
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"000000" & std_logic_vector(Sample+kSamplesPerClock-3) &
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"000000" & std_logic_vector(Sample+kSamplesPerClock-4) &
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"000000" & std_logic_vector(Sample+kSamplesPerClock-5) &
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"000000" & std_logic_vector(Sample+kSamplesPerClock-6) &
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"000000" & std_logic_vector(Sample+kSamplesPerClock-7) &
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"000000" & std_logic_vector(Sample+kSamplesPerClock-8) &
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"000000" & std_logic_vector(Sample+kSamplesPerClock-9) &
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"000000" & std_logic_vector(Sample+kSamplesPerClock-10) &
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"000000" & std_logic_vector(Sample+kSamplesPerClock-11) &
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"000000" & std_logic_vector(Sample+kSamplesPerClock-12);
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Sample := Sample +12;
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end if;
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end if;
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end process;
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-- Check if saturation and data packing is done correctly.
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DataCheck: process(Clk)
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variable Sample : Sample18_t := kSmallest18;
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variable ExpectedData : std_logic_vector(15 downto 0);
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begin
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if falling_edge(Clk) then
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if cDataValidOut then
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for i in 1 to 12 loop
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ExpectedData := tb_saturate(std_logic_vector(Sample));
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assert cDataOut(kSatDataWidth*i-1 downto kSatDataWidth*(i-1)) = ExpectedData
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report "Saturation data out mismatch in index : " & to_string(i) & LF &
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"Expected data is : " & to_hstring(ExpectedData) & LF &
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"Received data is : " & to_hstring(cDataOut(kSatDataWidth*i-1 downto kSatDataWidth*(i-1)))
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severity error;
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Sample := Sample+1;
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end loop;
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end if;
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end if;
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end process;
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end RTL;
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