49 lines
1.9 KiB
Tcl
49 lines
1.9 KiB
Tcl
#
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# Copyright 2024 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl
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source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl
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# STEP#1: Create project, add sources, refresh IP
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vivado_utils::initialize_project
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# STEP#2: Run synthesis
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vivado_utils::synthesize_design
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vivado_utils::generate_post_synth_reports
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# STEP#3: Run implementation strategy
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set x3xx_strategy [dict create]
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dict set x3xx_strategy "implementation.incremental" 0
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dict set x3xx_strategy "opt_design.is_enabled" 1
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dict set x3xx_strategy "opt_design.directive" "NoBramPowerOpt"
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dict set x3xx_strategy "post_opt_power_opt_design.is_enabled" 0
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dict set x3xx_strategy "place_design.directive" "ExtraNetDelay_high"
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dict set x3xx_strategy "post_place_power_opt_design.is_enabled" 0
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dict set x3xx_strategy "post_place_phys_opt_design.is_enabled" 1
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dict set x3xx_strategy "post_place_phys_opt_design.directive" "AggressiveExplore"
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dict set x3xx_strategy "route_design.directive" "Explore"
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dict set x3xx_strategy "route_design.more_options" "-tns_cleanup"
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dict set x3xx_strategy "post_route_phys_opt_design.is_enabled" 1
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dict set x3xx_strategy "post_route_phys_opt_design.directive" "Explore"
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vivado_strategies::implement_design $x3xx_strategy
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# STEP#4: Generate reports
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vivado_utils::generate_post_route_reports
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# STEP#5: Generate a bitstream, netlist and debug probes
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# STC3 Requirement: Disable waiting for DCI Match
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set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [get_designs *]
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# STC3 Requirement: No bitstream compression
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set_property BITSTREAM.GENERAL.COMPRESS False [get_designs *]
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# Use 6MHz clock to configure bitstream
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set_property BITSTREAM.CONFIG.CONFIGRATE 6 [get_designs *]
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vivado_utils::write_implementation_outputs
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# Cleanup
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vivado_utils::close_batch_project
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