Wade Fife
2487e7bdf8
Xilinx changed the way [all_registers -edge_triggered] is treated such that set_max_delay constraints that use it can cause segmentation and cause clocks to not be propagated to all endpoints. Changing to [all_ffs] avoids this potential issue. Original-commit: 55e422535292c29de00b80f15b0a49ca3fb94f26
158 lines
7.7 KiB
Tcl
158 lines
7.7 KiB
Tcl
#
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# Copyright 2018 Ettus Research, A National Instruments Company
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# SPDX-License-Identifier: LGPL-3.0
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#
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# Description: Timing constraints for the USRP E31X
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#
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###############################################################################
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# Input Clocks
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###############################################################################
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# 10MHz / PPS References
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create_clock -period 100.000 -name pps_ext [get_nets PPS_EXT_IN]
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create_clock -period 100.000 -name gps_pps [get_nets GPS_PPS]
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# TCXO clock 40 MHz
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create_clock -period 25.000 -name TCXO_CLK [get_nets TCXO_CLK]
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set_input_jitter TCXO_CLK 0.100
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###############################################################################
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# Rename Clocks
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###############################################################################
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create_clock -period 10.000 \
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-name bus_clk [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/FCLKCLK[0]}]
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set_input_jitter bus_clk 0.300
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create_clock -period 25.000 \
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-name clk40 [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/FCLKCLK[1]}]
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set_input_jitter clk40 0.750
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#create_clock -period 5.000 \
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# -name bus_clk [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/FCLKCLK[3]}]
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#set_input_jitter bus_clk 0.150
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###############################################################################
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# Timing Constraints for E310 daughter board signals
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###############################################################################
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# CAT_DATA_CLK is the data clock from AD9361, sample rate dependent with a max rate of 61.44 MHz
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set cat_data_clk_period 16.276;
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set cat_data_clk_duty_cycle_var [expr $cat_data_clk_period * (0.55 - 0.45)];
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set tcxo_jitter 0.0005; # Calculated from datasheet phase noise
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create_clock -period $cat_data_clk_period -name CAT_DATA_CLK [get_ports CAT_DATA_CLK]
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# Model variable duty cycle as jitter.
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set_input_jitter CAT_DATA_CLK [expr $cat_data_clk_duty_cycle_var + $tcxo_jitter]
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# Generate DAC output clock
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create_generated_clock -name CAT_FB_CLK -multiply_by 1 -source [get_pins e310_io/oddr_clk/C] [get_ports CAT_FB_CLK]
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# Asynchronous clock domains
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set_clock_groups -asynchronous \
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-group [get_clocks -include_generated_clocks CAT_DATA_CLK] \
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-group [get_clocks -include_generated_clocks bus_clk] \
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-group [get_clocks -include_generated_clocks TCXO_CLK]
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set_clock_groups -asynchronous \
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-group [get_clocks -include_generated_clocks *clk_200M_o] \
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-group [get_clocks -include_generated_clocks pps_ext] \
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-group [get_clocks -include_generated_clocks gps_pps]
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#TODO: I don't think this was getting used on E310
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# Logically exclusive clocks in catcodec capture interface. These two clocks are the input to a BUFG mux that
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# drives radio_clk, meaning only one of the two can drive radio_clk at a time.
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#set_clock_groups -logically_exclusive # -group [get_clocks -include_generated_clocks {clk0}] # -group [get_clocks -include_generated_clocks {clkdv}]
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# Setup ADC (AD9361) interface constraints.
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set cat_data_prog_dly 4.5; # Programmable skew in AD9361 set to delay RX data by 4.5 ns
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set cat_data_clk_to_data_out_min 0;
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set cat_data_clk_to_data_out_max 1.2;
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set_input_delay -clock [get_clocks CAT_DATA_CLK] -max [expr $cat_data_prog_dly + $cat_data_clk_to_data_out_max] [get_ports {CAT_P0_D* CAT_RX_FRAME}]
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set_input_delay -clock [get_clocks CAT_DATA_CLK] -min [expr $cat_data_prog_dly + $cat_data_clk_to_data_out_min] [get_ports {CAT_P0_D* CAT_RX_FRAME}]
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set_input_delay -clock [get_clocks CAT_DATA_CLK] -max [expr $cat_data_prog_dly + $cat_data_clk_to_data_out_max] [get_ports {CAT_P0_D* CAT_RX_FRAME}] -clock_fall -add_delay
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set_input_delay -clock [get_clocks CAT_DATA_CLK] -min [expr $cat_data_prog_dly + $cat_data_clk_to_data_out_min] [get_ports {CAT_P0_D* CAT_RX_FRAME}] -clock_fall -add_delay
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set cat_fb_data_prog_dly 4.5; # Programmable skew in AD9361 set to delay TX data by 4.5 ns
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set cat_fb_data_setup 1.0;
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set cat_fb_data_hold 0;
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set_output_delay -clock CAT_FB_CLK -max [expr $cat_fb_data_prog_dly + $cat_fb_data_setup] [get_ports {CAT_P1_D* CAT_TX_FRAME}]
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set_output_delay -clock CAT_FB_CLK -min [expr $cat_fb_data_prog_dly - $cat_fb_data_hold] [get_ports {CAT_P1_D* CAT_TX_FRAME}]
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set_output_delay -clock CAT_FB_CLK -max [expr $cat_fb_data_prog_dly + $cat_fb_data_setup] [get_ports {CAT_P1_D* CAT_TX_FRAME}] -clock_fall -add_delay;
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set_output_delay -clock CAT_FB_CLK -min [expr $cat_fb_data_prog_dly - $cat_fb_data_hold] [get_ports {CAT_P1_D* CAT_TX_FRAME}] -clock_fall -add_delay;
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# TODO: CAT SPI
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# Xilinx doesn't allow you to fully constrain EMIO because the internal SPI
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# clock is not accessible. So delay constraints are used to limit the delays to
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# compatible values.
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# Transceiver SPI
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set_max_delay -from [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0MO] \
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-to [get_ports CAT_MOSI] 10.000 -datapath_only
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set_min_delay -to [get_ports CAT_MOSI] 1.000
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#
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set_max_delay -from [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0SCLKO] \
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-to [get_ports CAT_SCLK] 10.000 -datapath_only
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set_min_delay -to [get_ports CAT_SCLK] 1.000
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#
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set_max_delay -from [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0SSON[0]}] \
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-to [get_ports CAT_CS] 10.000 -datapath_only
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set_min_delay -to [get_ports CAT_CS] 1.000
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#
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set_max_delay -from [get_ports CAT_MISO] \
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-to [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 10.000 -datapath_only
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set_min_delay -from [get_ports CAT_MISO] \
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-to [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 1.000
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###############################################################################
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# PPS and Ref Clk Input Timing
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###############################################################################
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# Asynchronous clock domains
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set_clock_groups -asynchronous \
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-group [get_clocks -include_generated_clocks bus_clk] \
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-group [get_clocks -include_generated_clocks pps_ext] \
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-group [get_clocks -include_generated_clocks gps_pps]
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# TCXO DAC SPI
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# 12 MHz SPI clock rate
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set_max_delay -datapath_only -from [all_ffs] -to [get_ports TCXO_DAC*] 40.000
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set_min_delay -from [all_ffs] -to [get_ports TCXO_DAC*] 1.000
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# User GPIO
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set_max_delay -datapath_only -to [get_ports PL_GPIO*] -from [all_ffs] [expr 15.0]
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set_min_delay -to [get_ports PL_GPIO*] -from [all_ffs] 5.0
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set_max_delay -datapath_only -from [get_ports PL_GPIO*] -to [all_ffs] [expr 15.0]
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set_min_delay -from [get_ports PL_GPIO*] -to [all_ffs] 5.0
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# GPIO muxing
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set_max_delay -from [get_pins e31x_core_inst/fp_gpio_src_reg_reg[*]/C] -to [get_clocks CAT_DATA_CLK] $cat_data_clk_period -datapath_only
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###############################################################################
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# False Paths
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###############################################################################
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# Synchronizer core false paths
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set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/D}]
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set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/S}]
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# USR_ACCESS build date
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set_false_path -through [get_pins {usr_access_i/DATA[*]}]
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###############################################################################
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## Asynchronous paths
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###############################################################################
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set_false_path -from [get_ports CAT_CTRL_OUT]
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set_false_path -to [get_ports CAT_RESET]
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set_false_path -to [get_ports RX*_BANDSEL*]
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set_false_path -to [get_ports TX_BANDSEL*]
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set_false_path -to [get_ports TX_ENABLE*]
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set_false_path -to [get_ports LED_*]
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set_false_path -to [get_ports VCRX*]
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set_false_path -to [get_ports VCTX*]
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set_false_path -from [get_ports ONSWITCH_DB]
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