474 lines
13 KiB
Verilog
474 lines
13 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//
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// Copyright 2018-2019 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: e31x
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// Description:
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// E31x Top Level Idle
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//
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/////////////////////////////////////////////////////////////////////
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module e31x (
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// PS Connections
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inout [53:0] MIO,
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input PS_SRSTB,
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input PS_CLK,
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input PS_PORB,
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inout DDR_CLK,
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inout DDR_CLK_N,
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inout DDR_CKE,
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inout DDR_CS_N,
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inout DDR_RAS_N,
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inout DDR_CAS_N,
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inout DDR_WEB,
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inout [2:0] DDR_BANKADDR,
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inout [14:0] DDR_ADDR,
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inout DDR_ODT,
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inout DDR_DRSTB,
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inout [31:0] DDR_DQ,
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inout [3:0] DDR_DM,
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inout [3:0] DDR_DQS,
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inout [3:0] DDR_DQS_N,
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inout DDR_VRP,
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inout DDR_VRN,
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//AVR SPI IO
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input AVR_CS_R,
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output AVR_IRQ,
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output AVR_MISO_R,
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input AVR_MOSI_R,
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input AVR_SCK_R,
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input ONSWITCH_DB,
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// pps connections
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input GPS_PPS,
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input PPS_EXT_IN,
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// gpios, change to inout somehow
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inout [5:0] PL_GPIO,
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// RF Board connections
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inout [99:0] DB_IO
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);
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// Clocks
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wire bus_clk;
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wire radio_clk;
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wire reg_clk;
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wire clk40;
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wire FCLK_CLK0;
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wire FCLK_CLK1;
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// Resets
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wire global_rst;
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wire bus_rst;
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wire radio_rst;
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wire reg_rstn;
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wire clk40_rst;
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wire clk40_rstn;
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wire FCLK_RESET0_N;
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// PMU
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wire [31:0] m_axi_pmu_araddr;
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wire [2:0] m_axi_pmu_arprot;
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wire m_axi_pmu_arready;
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wire m_axi_pmu_arvalid;
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wire [31:0] m_axi_pmu_awaddr;
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wire [2:0] m_axi_pmu_awprot;
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wire m_axi_pmu_awready;
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wire m_axi_pmu_awvalid;
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wire m_axi_pmu_bready;
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wire [1:0] m_axi_pmu_bresp;
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wire m_axi_pmu_bvalid;
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wire [31:0] m_axi_pmu_rdata;
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wire m_axi_pmu_rready;
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wire [1:0] m_axi_pmu_rresp;
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wire m_axi_pmu_rvalid;
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wire [31:0] m_axi_pmu_wdata;
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wire m_axi_pmu_wready;
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wire [3:0] m_axi_pmu_wstrb;
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wire m_axi_pmu_wvalid;
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/////////////////////////////////////////////////////////////////////
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//
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// Resets:
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// - PL - Bus Reset
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// Radio Reset
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// - PS - FCLK_RESET0_N --> clk40_rst(n)
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//
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//////////////////////////////////////////////////////////////////////
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// Synchronous reset for the bus_clk domain
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reset_sync bus_reset_gen (
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.clk(bus_clk),
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.reset_in(~FCLK_RESET0_N),
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//.reset_in(~clocks_locked),
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.reset_out(bus_rst)
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);
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// PS-based Resets //
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//
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// Synchronous reset for the clk40 domain. This is derived from the PS reset 0.
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reset_sync clk40_reset_gen (
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.clk(clk40),
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.reset_in(~FCLK_RESET0_N),
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.reset_out(clk40_rst)
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);
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// Invert for various modules.
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assign clk40_rstn = ~clk40_rst;
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assign reg_rstn = clk40_rstn;
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/////////////////////////////////////////////////////////////////////
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//
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// Clocks and PPS
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//
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/////////////////////////////////////////////////////////////////////
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wire [1:0] pps_select;
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assign clk40 = FCLK_CLK1; // 40 MHz
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assign bus_clk = FCLK_CLK0; // 100 MHz
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assign reg_clk = clk40;
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reg [2:0] pps_reg;
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wire pps_ext = PPS_EXT_IN;
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wire gps_pps = GPS_PPS;
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// connect PPS input to GPIO so ntpd can use it
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always @ (posedge bus_clk)
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pps_reg <= bus_rst ? 3'b000 : {pps_reg[1:0], GPS_PPS};
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assign ps_gpio_in[8] = pps_reg[2]; // 62
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/////////////////////////////////////////////////////////////////////
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//
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// Power Button
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//
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//////////////////////////////////////////////////////////////////////
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// register the debounced onswitch signal to detect edges,
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// Note: ONSWITCH_DB is low active
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reg [1:0] onswitch_edge;
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always @ (posedge bus_clk)
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onswitch_edge <= bus_rst ? 2'b00 : {onswitch_edge[0], ONSWITCH_DB};
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wire button_press = ~ONSWITCH_DB & onswitch_edge[0] & onswitch_edge[1];
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wire button_release = ONSWITCH_DB & ~onswitch_edge[0] & ~onswitch_edge[1];
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// stretch the pulse so IRQs don't get lost
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reg [7:0] button_press_reg, button_release_reg;
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always @ (posedge bus_clk)
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if (bus_rst) begin
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button_press_reg <= 8'h00;
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button_release_reg <= 8'h00;
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end else begin
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button_press_reg <= {button_press_reg[6:0], button_press};
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button_release_reg <= {button_release_reg[6:0], button_release};
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end
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wire button_press_irq = |button_press_reg;
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wire button_release_irq = |button_release_reg;
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/////////////////////////////////////////////////////////////////////
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//
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// Interrupts Fabric to PS
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//
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//////////////////////////////////////////////////////////////////////
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wire [15:0] IRQ_F2P;
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wire pmu_irq;
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assign IRQ_F2P = {12'b0,
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pmu_irq, // Interrupt 32
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button_release_irq, // Interrupt 31
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button_press_irq, // Interrupt 30
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1'b0};
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/////////////////////////////////////////////////////////////////////
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//
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// PS Connections
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//
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//////////////////////////////////////////////////////////////////////
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wire [63:0] ps_gpio_in;
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wire [63:0] ps_gpio_out;
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wire [63:0] ps_gpio_tri;
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e31x_ps_bd e31x_ps_bd_inst (
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// DDR Interface
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.DDR_VRN(DDR_VRN),
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.DDR_VRP(DDR_VRP),
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.DDR_addr(DDR_ADDR),
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.DDR_ba(DDR_BANKADDR),
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.DDR_cas_n(DDR_CAS_N),
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.DDR_ck_n(DDR_CLK_N),
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.DDR_ck_p(DDR_CLK),
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.DDR_cke(DDR_CKE),
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.DDR_cs_n(DDR_CS_N),
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.DDR_dm(DDR_DM),
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.DDR_dq(DDR_DQ),
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.DDR_dqs_n(DDR_DQS_N),
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.DDR_dqs_p(DDR_DQS),
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.DDR_odt(DDR_ODT),
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.DDR_ras_n(DDR_RAS_N),
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.DDR_reset_n(DDR_RESET_N),
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.DDR_we_n(DDR_WE_N),
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// Clocks
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.FCLK_CLK0(FCLK_CLK0),
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.FCLK_CLK1(FCLK_CLK1),
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.FCLK_CLK2(),
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.FCLK_CLK3(),
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// Resets
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.FCLK_RESET0_N(FCLK_RESET0_N),
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// GPIO
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.GPIO_0_tri_i(ps_gpio_in),
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.GPIO_0_tri_o(ps_gpio_out),
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.GPIO_0_tri_t(ps_gpio_tri),
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// Interrupts
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.IRQ_F2P(IRQ_F2P),
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// MIO
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.MIO(MIO),
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.PS_CLK(PS_CLK),
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.PS_PORB(PS_PORB),
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.PS_SRSTB(PS_SRSTB),
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// SPI
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.SPI0_MISO_I(),
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.SPI0_MISO_O(),
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.SPI0_MISO_T(),
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.SPI0_MOSI_I(),
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.SPI0_MOSI_O(),
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.SPI0_MOSI_T(),
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.SPI0_SCLK_I(),
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.SPI0_SCLK_O(),
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.SPI0_SCLK_T(),
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.SPI0_SS1_O(),
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.SPI0_SS2_O(),
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.SPI0_SS_I(),
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.SPI0_SS_O(),
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.SPI0_SS_T(),
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.SPI1_MISO_I(),
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.SPI1_MISO_O(),
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.SPI1_MISO_T(),
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.SPI1_MOSI_I(),
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.SPI1_MOSI_O(),
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.SPI1_MOSI_T(),
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.SPI1_SCLK_I(),
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.SPI1_SCLK_O(),
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.SPI1_SCLK_T(),
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.SPI1_SS1_O(),
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.SPI1_SS2_O(),
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.SPI1_SS_I(),
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.SPI1_SS_O(),
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.SPI1_SS_T(),
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// USB
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.USBIND_0_port_indctl(),
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.USBIND_0_vbus_pwrfault(),
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.USBIND_0_vbus_pwrselect(),
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.bus_clk(bus_clk),
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.bus_rstn(~bus_rst),
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.clk40(clk40),
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.clk40_rstn(clk40_rstn),
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.S_AXI_GP0_ACLK(clk40),
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.S_AXI_GP0_ARESETN(clk40_rstn),
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// XBAR Regport
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.m_axi_xbar_araddr(),
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.m_axi_xbar_arprot(),
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.m_axi_xbar_arready(),
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.m_axi_xbar_arvalid(),
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.m_axi_xbar_awaddr(),
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.m_axi_xbar_awprot(),
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.m_axi_xbar_awready(),
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.m_axi_xbar_awvalid(),
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.m_axi_xbar_bready(),
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.m_axi_xbar_bresp(),
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.m_axi_xbar_bvalid(),
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.m_axi_xbar_rdata(),
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.m_axi_xbar_rready(),
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.m_axi_xbar_rresp(),
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.m_axi_xbar_rvalid(),
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.m_axi_xbar_wdata(),
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.m_axi_xbar_wready(),
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.m_axi_xbar_wstrb(),
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.m_axi_xbar_wvalid(),
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// PMU
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.m_axi_pmu_araddr(m_axi_pmu_araddr),
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.m_axi_pmu_arprot(m_axi_pmu_arprot),
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.m_axi_pmu_arready(m_axi_pmu_arready),
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.m_axi_pmu_arvalid(m_axi_pmu_arvalid),
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.m_axi_pmu_awaddr(m_axi_pmu_awaddr),
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.m_axi_pmu_awprot(m_axi_pmu_awprot),
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.m_axi_pmu_awready(m_axi_pmu_awready),
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.m_axi_pmu_awvalid(m_axi_pmu_awvalid),
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.m_axi_pmu_bready(m_axi_pmu_bready),
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.m_axi_pmu_bresp(m_axi_pmu_bresp),
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.m_axi_pmu_bvalid(m_axi_pmu_bvalid),
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.m_axi_pmu_rdata(m_axi_pmu_rdata),
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.m_axi_pmu_rready(m_axi_pmu_rready),
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.m_axi_pmu_rresp(m_axi_pmu_rresp),
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.m_axi_pmu_rvalid(m_axi_pmu_rvalid),
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.m_axi_pmu_wdata(m_axi_pmu_wdata),
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.m_axi_pmu_wready(m_axi_pmu_wready),
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.m_axi_pmu_wstrb(m_axi_pmu_wstrb),
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.m_axi_pmu_wvalid(m_axi_pmu_wvalid),
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// DMA
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.s_axis_dma_tdata(),
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.s_axis_dma_tkeep(),
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.s_axis_dma_tlast(),
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.s_axis_dma_tready(),
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.s_axis_dma_tvalid(1'b0),
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.m_axis_dma_tdata(),
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.m_axis_dma_tkeep(),
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.m_axis_dma_tlast(),
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.m_axis_dma_tready(1'b1),
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.m_axis_dma_tvalid()
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);
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/////////////////////////////////////////////////////////////////////
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//
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// PMU
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//
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//////////////////////////////////////////////////////////////////////
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axi_pmu inst_axi_pmu (
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.s_axi_aclk(clk40), // TODO: Original design used bus_clk
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.s_axi_areset(clk40_rst),
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.ss(AVR_CS_R),
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.mosi(AVR_MOSI_R),
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.sck(AVR_SCK_R),
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.miso(AVR_MISO_R),
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// AXI4-Lite: Write address port (domain: s_axi_aclk)
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.s_axi_awaddr(m_axi_pmu_awaddr),
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.s_axi_awvalid(m_axi_pmu_awvalid),
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.s_axi_awready(m_axi_pmu_awready),
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// AXI4-Lite: Write data port (domain: s_axi_aclk)
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.s_axi_wdata(m_axi_pmu_wdata),
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.s_axi_wstrb(m_axi_pmu_wstrb),
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.s_axi_wvalid(m_axi_pmu_wvalid),
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.s_axi_wready(m_axi_pmu_wready),
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// AXI4-Lite: Write response port (domain: s_axi_aclk)
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.s_axi_bresp(m_axi_pmu_bresp),
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.s_axi_bvalid(m_axi_pmu_bvalid),
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.s_axi_bready(m_axi_pmu_bready),
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// AXI4-Lite: Read address port (domain: s_axi_aclk)
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.s_axi_araddr(m_axi_pmu_araddr),
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.s_axi_arvalid(m_axi_pmu_arvalid),
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.s_axi_arready(m_axi_pmu_arready),
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// AXI4-Lite: Read data port (domain: s_axi_aclk)
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.s_axi_rdata(m_axi_pmu_rdata),
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.s_axi_rresp(m_axi_pmu_rresp),
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.s_axi_rvalid(m_axi_pmu_rvalid),
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.s_axi_rready(m_axi_pmu_rready),
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.s_axi_irq(pmu_irq)
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);
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assign AVR_IRQ = 1'b0;
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localparam DB_E31X_IDLE_OUT = {
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1'b0, /* DB_EXP_18_24 (99) */
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13'b0000000000000, /* leds & rx bandsels */
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1'b0, /* CAT_FB_CLK (85) */
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1'b0, /* CAT_TX_FRAME (84) */
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1'b0, /* CAT_RX_DATA_CLK (83) */
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25'b0000_0000_0000_0000_0000_0000_0, /* CAT_RX_FRAME(81), CAT_P0 & CAT_P1 (58)*/
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1'b0, /* CAT_SYNC(57) */
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4'b0000, /* CAT_ENAGC(56), CAT_BBCLK_OUT (55), CAT_ENABLE(54), CAT_TXNRX(53) */
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3'b000, /* DB_EXP_1_8_V_{33,34,32} */
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2'b00, /* CAT_CTRL_IN[1:0] (49,48) */
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1'b0, /* CAT_MISO (47) */
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4'b0000, /* CAT_{MOSI,SCLK,CS,RESETn) (46,45, 44, 43) */
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1'b0, /* DB_1_8V_31 (42) */
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8'h00, /* CAT_CTRL_OUT (41:34) */
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1'b0, /* DB_1_8V_11 (33) */
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1'b0, /* CAT_CTRL_IN3 (32) */
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1'b0, /* DB_1_8V_10 (31) */
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1'b0, /* CAT_CTRL_IN2 (30) */
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1'b0, /* DB_1_8V_9 (29) */
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1'b0, /* VCRX2_V2 (28) */
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1'b0, /* DB_1_8V_8 (25) */
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1'b0, /* VCRX2_V1 (26) */
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1'b0, /* DB_1_8V_7 (25) */
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1'b0, /* VCRX1_V2 (24) */
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1'b0, /* DB_1_8V_6 (23) */
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1'b0, /* VCRX1_V1 (22) */
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1'b0, /* DB_1_8V_5 (21) */
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1'b0, /* VCTXRX1_V2 (20) */
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1'b0, /* DB_1_8V_4 (19) */
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1'b0, /* VCTXRX1_V1 (18) */
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1'b0, /* DB_1_8V_3 (17) */
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1'b0, /* VCTXRX2_V1 (16) */
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1'b1, /* DB_1_8V_2 (15) */
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15'd0};
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localparam DB_E31X_IDLE_DDR = {
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1'b0, /* DB_EXP_18_24 (99) */
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13'b0101010101010, /* leds & rx bandsels */
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1'b0, /* CAT_FB_CLK (85) */
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1'b0, /* CAT_TX_FRAME (84) */
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1'b0, /* CAT_RX_DATA_CLK (83) */
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25'b0000_0000_0000_0000_0000_0000_0, /* CAT_RX_FRAME(81), CAT_P0 & CAT_P1 (58) */
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1'b0, /* CAT_SYNC(57) */
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4'b0001, /* CAT_ENAGC(56), CAT_BBCLK_OUT (55), CAT_ENABLE(54), CAT_TXNRX(53) */
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3'b000, /* DB_EXP_1_8_V_{32,33,34,} (52, 51, 50) */
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2'b00, /* CAT_CTRL_IN[1:0] (49,48) */
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1'b0, /* CAT_MISO (47) */
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4'b0111, /* CAT_{MOSI,SCLK,CS,RESETn) (46, 45, 44, 43) */
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1'b0, /* DB_1_8V_31 (42) */
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8'h00, /* CAT_CTRL_OUT (41:34) */
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1'b0, /* DB_1_8V_11 (33) */
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1'b0, /* CAT_CTRL_IN3 (32) */
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1'b0, /* DB_1_8V_10 (31) */
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1'b0, /* CAT_CTRL_IN2 (30) */
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1'b0, /* DB_1_8V_9 (29) */
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1'b0, /* VCRX2_V2 (28) */
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1'b0, /* DB_1_8V_8 (25) */
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1'b0, /* VCRX2_V1 (26) */
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1'b0, /* DB_1_8V_7 (24) */
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1'b0, /* VCRX1_V2 (24) */
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1'b0, /* DB_1_8V_6 (23) */
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1'b0, /* VCRX1_V1 (22) */
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1'b0, /* DB_1_8V_5 (21) */
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1'b0, /* VCTXRX1_V1 (20) */
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1'b0, /* DB_1_8V_4 (19) */
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1'b0, /* VCTXRX1_V2 (18) */
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1'b1, /* DB_1_8V_3 (17) */
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1'b0, /* VCTXRX2_V1 (16) */
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1'b1, /* DB_1_8V_2 (15) */
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15'd0};
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localparam NUM_DB_IO_PINS = 100;
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wire [NUM_DB_IO_PINS-1:0] db_ddr = DB_E31X_IDLE_DDR;
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wire [NUM_DB_IO_PINS-1:0] db_out = DB_E31X_IDLE_OUT;
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wire [NUM_DB_IO_PINS-1:0] db_in;
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genvar k;
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generate
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for (k = 0; k < NUM_DB_IO_PINS; k = k+1) begin
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IOBUF db_io_i(.O(db_in[k]), .IO(DB_IO[k]), .I(db_out[k]), .T(~db_ddr[k]));
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end
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endgenerate
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endmodule // e31x
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