70 lines
2.1 KiB
Verilog
70 lines
2.1 KiB
Verilog
//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_resp_combine
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//
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// Description:
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//
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// This module combines the control-port responses from multiple slave blocks
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// into a single response for the master. This is done by using ack bit to
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// mask all bits of the responses then ORing all the results together onto a
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// single response bus. This is valid because only one block is allowed to
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// respond to a single request.
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//
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// Note that no special logic is required to split the requests from the
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// master among multiple slaves. A single master request interface can be
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// directly connected to all the slaves without issue.
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//
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// Parameters:
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//
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// NUM_SLAVES : The number of slaves you want to connect to a master.
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//
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module ctrlport_resp_combine #(
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parameter NUM_SLAVES = 2
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) (
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Responses from multiple slaves
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input wire [ NUM_SLAVES-1:0] m_ctrlport_resp_ack,
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input wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
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input wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data,
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// Response to a single master
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output reg s_ctrlport_resp_ack,
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output reg [ 1:0] s_ctrlport_resp_status,
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output reg [31:0] s_ctrlport_resp_data
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);
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always @(posedge ctrlport_clk) begin : or_reg_resp
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reg [31:0] data;
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reg [ 1:0] status;
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reg ack;
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integer s;
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// Take the responses and mask them with ack then OR them together
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data = 0;
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status = 0;
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ack = 0;
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for (s = 0; s < NUM_SLAVES; s = s+1) begin
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data = data | (m_ctrlport_resp_data [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
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status = status | (m_ctrlport_resp_status[s* 2 +: 2] & { 2{m_ctrlport_resp_ack[s]}});
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ack = ack | m_ctrlport_resp_ack[s];
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end
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// Register the output to break combinatorial path
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s_ctrlport_resp_data <= data;
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s_ctrlport_resp_status <= status;
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s_ctrlport_resp_ack <= ack;
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if (ctrlport_rst) begin
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s_ctrlport_resp_ack <= 0;
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end
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end
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endmodule
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