Wade Fife
d671f408c0
This adds a parameter to chdr_xb_ingress_buff and to chdr_stream_output to make their packet gates optional. They are included by default. Having the packet gate in chdr_xb_ingress_buff can reduce contention in the crossbar. Having the packet gate in chdr_stream_output can reduce the latency for non-data packets (e.g., stream status updates). Original-commit: 67e0a5a340c14cb0c6ee170fb17be2c09737d723
587 lines
21 KiB
Verilog
587 lines
21 KiB
Verilog
//
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// Copyright 2018-2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: chdr_stream_output
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// Description:
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// Implements the CHDR output port for a stream endpoint.
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// The module generates stream command packets to setup
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// a downstream endpoint module (chdr_stream_input). Once
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// a stream is setup, the CHDR data on the axis_data port
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// can be sent downstream with full flow control. Stream
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// status messages are received from the downstream node
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// to update flow control state. This module has an external
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// configuration bus to initiate stream creation.
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//
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// Parameters:
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// - CHDR_W : Width of the CHDR bus in bits
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// - MTU : Log2 of the maximum number of lines in a packet
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// - EN_PKT_GATE : Enable packet gate to make each packet contiguous
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//
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// Signals:
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// - m_axis_chdr_* : Output CHDR stream (AXI-Stream)
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// - s_axis_data_* : Input CHDR Data stream (AXI-Stream) before flow control
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// - s_axis_strs_* : Input stream status (AXI-Stream)
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module chdr_stream_output #(
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parameter CHDR_W = 256,
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parameter MTU = 10,
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parameter EN_PKT_GATE = 1
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)(
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// Clock, reset and settings
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input wire clk,
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input wire rst,
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// CHDR out (AXI-Stream)
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output wire [CHDR_W-1:0] m_axis_chdr_tdata,
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output wire m_axis_chdr_tlast,
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output wire m_axis_chdr_tvalid,
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input wire m_axis_chdr_tready,
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// Data packets in (AXI-Stream)
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input wire [CHDR_W-1:0] s_axis_data_tdata,
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input wire s_axis_data_tlast,
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input wire s_axis_data_tvalid,
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output wire s_axis_data_tready,
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// Stream status in (AXI-Stream)
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input wire [CHDR_W-1:0] s_axis_strs_tdata,
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input wire s_axis_strs_tlast,
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input wire s_axis_strs_tvalid,
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output wire s_axis_strs_tready,
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// Configuration port
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input wire cfg_start,
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output reg cfg_pending = 1'b0,
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output reg cfg_failed = 1'b0,
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input wire cfg_lossy_xport,
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input wire [15:0] cfg_dst_epid,
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input wire [15:0] cfg_this_epid,
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input wire [39:0] cfg_fc_freq_bytes,
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input wire [23:0] cfg_fc_freq_pkts,
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input wire [15:0] cfg_fc_headroom_bytes,
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input wire [7:0] cfg_fc_headroom_pkts,
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// Flow control status
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output reg fc_enabled = 1'b0,
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output reg [39:0] capacity_bytes = 40'd0,
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output reg [23:0] capacity_pkts = 24'd0,
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// Stream status
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output wire seq_err_stb,
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output reg [31:0] seq_err_cnt = 32'd0,
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output wire data_err_stb,
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output reg [31:0] data_err_cnt = 32'd0,
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output wire route_err_stb,
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output reg [31:0] route_err_cnt = 32'd0
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);
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// ---------------------------------------------------
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// RFNoC Includes
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// ---------------------------------------------------
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`include "rfnoc_chdr_utils.vh"
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`include "rfnoc_chdr_internal_utils.vh"
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localparam CHDR_W_LOG2 = $clog2(CHDR_W);
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// ---------------------------------------------------
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// Output packet gate
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// ---------------------------------------------------
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reg [CHDR_W-1:0] chdr_out_tdata;
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reg chdr_out_tlast, chdr_out_tvalid;
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wire chdr_out_tready;
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if (EN_PKT_GATE) begin : gen_pkt_gate
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axi_packet_gate #(
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.WIDTH (CHDR_W),
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.SIZE (MTU ),
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.USE_AS_BUFF(0 )
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) chdr_pkt_gate_i (
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.clk (clk ),
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.reset (rst ),
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.clear (1'b0 ),
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.i_tdata (chdr_out_tdata ),
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.i_tlast (chdr_out_tlast ),
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.i_terror(1'b0 ),
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.i_tvalid(chdr_out_tvalid ),
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.i_tready(chdr_out_tready ),
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.o_tdata (m_axis_chdr_tdata ),
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.o_tlast (m_axis_chdr_tlast ),
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.o_tvalid(m_axis_chdr_tvalid),
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.o_tready(m_axis_chdr_tready)
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);
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end else begin : gen_no_pkt_gate
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assign m_axis_chdr_tdata = chdr_out_tdata;
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assign m_axis_chdr_tlast = chdr_out_tlast;
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assign m_axis_chdr_tvalid = chdr_out_tvalid;
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assign chdr_out_tready = m_axis_chdr_tready;
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end
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// ---------------------------------------------------
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// Flow Control State
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// ---------------------------------------------------
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// send_cnt: Total transfer count at the sender (here)
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// recv_cnt: Total transfer count at the receiver
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// accum: Transfer count since last FC resynchronization request
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// headroom: Total headroom to keep in the downstream buffer
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// adj_cap: The adjusted capacity (after headroom) of the downstream buffer
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// strc_cnt: Saved count for the STRC packet (prevents mid-packet updates)
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reg [63:0] send_cnt_bytes = 64'd0;
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reg [39:0] send_cnt_pkts = 40'd0;
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reg [63:0] recv_cnt_bytes = 64'd0;
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reg [39:0] recv_cnt_pkts = 40'd0;
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reg [39:0] accum_bytes = 40'd0;
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reg [23:0] accum_pkts = 24'd0;
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reg [15:0] headroom_bytes = 16'd0;
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reg [ 7:0] headroom_pkts = 8'd0;
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reg [39:0] adj_cap_bytes = 40'd0;
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reg [23:0] adj_cap_pkts = 24'd0;
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reg [63:0] strc_cnt_bytes = 64'd0;
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// Output transfer count
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always @(posedge clk) begin
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if (rst || !fc_enabled) begin
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send_cnt_bytes <= 64'd0;
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send_cnt_pkts <= 40'd0;
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end else if (chdr_out_tvalid && chdr_out_tready) begin
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send_cnt_bytes <= send_cnt_bytes + (CHDR_W/8);
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if (chdr_out_tlast)
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send_cnt_pkts <= send_cnt_pkts + 40'd1;
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end
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end
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// Buffer occupied counts
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// TODO: Need better overflow handling
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wire signed [64:0] occupied_bytes =
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$signed({1'b0, send_cnt_bytes}) - $signed({1'b0, recv_cnt_bytes});
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wire signed [40:0] occupied_pkts =
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$signed({1'b0, send_cnt_pkts}) - $signed({1'b0, recv_cnt_pkts});
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// OK-to-Send shift register
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// - Why a shift-register here?
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// To allow the tools to re-time the wide comparators.
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// - We don't care about the latency here because stream
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// status messages are asynchronous wrt the data
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reg [3:0] ok_shreg = 4'b1111; // OK to send? (shift register)
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always @(posedge clk) begin
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if (rst || !fc_enabled) begin
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ok_shreg <= 4'b1111;
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end else begin
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ok_shreg <= {ok_shreg[2:0], (
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(occupied_bytes[40:0] < $signed({1'b0, adj_cap_bytes})) &&
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(occupied_pkts [24:0] < $signed({1'b0, adj_cap_pkts }))
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)};
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end
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end
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wire ok_to_send = ok_shreg[3];
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// Accumulated transfer count updater for FC resync
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reg lossy_xport = 1'b0;
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reg [3:0] fc_resync_req_shreg = 4'h0;
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wire fc_resync_req, fc_resync_ack;
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always @(posedge clk) begin
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if (rst || !fc_enabled || !lossy_xport || fc_resync_ack) begin
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// Reset
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accum_bytes <= 40'd0;
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accum_pkts <= 24'd0;
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fc_resync_req_shreg <= 4'b0000;
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end else begin
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if (chdr_out_tvalid && chdr_out_tready) begin
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// Count
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accum_bytes <= accum_bytes + (CHDR_W/8);
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if (chdr_out_tlast)
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accum_pkts <= accum_pkts + 24'd1;
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end
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// FC resync request
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fc_resync_req_shreg <= {fc_resync_req_shreg[2:0],
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(accum_bytes > capacity_bytes) || (accum_pkts > capacity_pkts)};
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end
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end
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assign fc_resync_req = fc_resync_req_shreg[3];
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// ---------------------------------------------------
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// Stream Status Parser
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// ---------------------------------------------------
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wire [3:0] msg_i_tdata, msg_o_tdata;
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wire msg_i_tvalid, msg_o_tvalid;
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wire msg_i_tready, msg_o_tready;
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axi_fifo #(.WIDTH(4), .SIZE(1)) msg_fifo_i (
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.clk(clk), .reset(rst), .clear(1'b0),
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.i_tdata(msg_i_tdata), .i_tvalid(msg_i_tvalid), .i_tready(msg_i_tready),
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.o_tdata(msg_o_tdata), .o_tvalid(msg_o_tvalid), .o_tready(msg_o_tready),
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.space(), .occupied()
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);
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localparam [2:0] ST_STRS_HDR = 3'd0; // Receiving the CHDR header of a stream status msg
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localparam [2:0] ST_STRS_W0 = 3'd1; // Receiving the first word of a stream status msg
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localparam [2:0] ST_STRS_W1 = 3'd2; // Receiving the second word of a stream status msg
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localparam [2:0] ST_STRS_W2 = 3'd3; // Receiving the third word of a stream status msg
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localparam [2:0] ST_STRS_W3 = 3'd4; // Receiving the fourth word of a stream status msg
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localparam [2:0] ST_STRS_LATCH = 3'd5; // Atomically updating and posting the status msg
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localparam [2:0] ST_STRS_DROP = 3'd6; // Something went wrong dropping current packet
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reg [2:0] strs_state = ST_STRS_HDR;
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reg strs_too_long = 1'b0;
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reg [15:0] cached_dst_epid = 16'd0;
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reg [255:0] cached_strs_msg;
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always @(posedge clk) begin
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if (rst) begin
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strs_state <= ST_STRS_HDR;
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strs_too_long <= 1'b0;
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end else begin
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case (strs_state)
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// ST_STRS_HDR
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// ------------------
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ST_STRS_HDR: begin
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if (s_axis_strs_tvalid) begin
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// Only accept stream status packets. Drop everything else
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if (chdr_get_pkt_type(s_axis_strs_tdata[63:0]) == CHDR_PKT_TYPE_STRS)
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strs_state <= ST_STRS_W0;
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else
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strs_state <= ST_STRS_DROP;
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strs_too_long <= 1'b0;
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end
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end
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// ST_STRS_W0
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// ------------------
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// - Cache the first word of the stream status
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// - For CHDR_W == 64, this is one of 4 words.
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// - For CHDR_W == 128, this is one of 2 words.
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// - For CHDR_W >= 256, this is the only word.
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ST_STRS_W0: begin
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if (s_axis_strs_tvalid) begin
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if (CHDR_W == 64) begin
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cached_strs_msg[63:0] <= s_axis_strs_tdata[63:0];
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strs_state <= !s_axis_strs_tlast ? ST_STRS_W1 : ST_STRS_HDR;
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end else if (CHDR_W == 128) begin
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cached_strs_msg[127:0] <= s_axis_strs_tdata[127:0];
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strs_state <= !s_axis_strs_tlast ? ST_STRS_W1 : ST_STRS_HDR;
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end else begin //CHDR_W >= 256
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cached_strs_msg[255:0] <= s_axis_strs_tdata[255:0];
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strs_state <= ST_STRS_LATCH;
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strs_too_long <= !s_axis_strs_tlast;
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end
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end
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end
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// ST_STRS_W1
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// ------------------
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// - Cache the second word of the stream status
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ST_STRS_W1: begin
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if (s_axis_strs_tvalid) begin
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if (CHDR_W == 64) begin
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cached_strs_msg[127:64] <= s_axis_strs_tdata[63:0];
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strs_state <= !s_axis_strs_tlast ? ST_STRS_W2 : ST_STRS_HDR;
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end else begin //CHDR_W >= 128
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cached_strs_msg[255:128] <= s_axis_strs_tdata[127:0];
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strs_state <= ST_STRS_LATCH;
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strs_too_long <= !s_axis_strs_tlast;
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end
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end
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end
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// ST_STRS_W2
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// ------------------
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// - Cache the third word of the stream status
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ST_STRS_W2: begin
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if (s_axis_strs_tvalid) begin
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cached_strs_msg[191:128] <= s_axis_strs_tdata[63:0];
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strs_state <= !s_axis_strs_tlast ? ST_STRS_W3 : ST_STRS_HDR;
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end
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end
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// ST_STRS_W3
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// ------------------
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// - Cache the fourth word of the stream status
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ST_STRS_W3: begin
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if (s_axis_strs_tvalid) begin
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cached_strs_msg[255:192] <= s_axis_strs_tdata[63:0];
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strs_state <= ST_STRS_LATCH;
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strs_too_long <= !s_axis_strs_tlast;
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end
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end
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// ST_STRS_LATCH
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// ------------------
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// - Act on the received stream status
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ST_STRS_LATCH: begin
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capacity_bytes <= chdr256_strs_get_capacity_bytes(cached_strs_msg);
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capacity_pkts <= chdr256_strs_get_capacity_pkts(cached_strs_msg);
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recv_cnt_bytes <= chdr256_strs_get_xfercnt_bytes(cached_strs_msg);
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recv_cnt_pkts <= chdr256_strs_get_xfercnt_pkts(cached_strs_msg);
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adj_cap_bytes <= chdr256_strs_get_capacity_bytes(cached_strs_msg) -
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{24'd0, headroom_bytes[15:(CHDR_W_LOG2-3)], {(CHDR_W_LOG2-3){1'b0}}};
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adj_cap_pkts <= chdr256_strs_get_capacity_pkts(cached_strs_msg) -
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{16'd0, headroom_pkts};
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if (msg_i_tready) begin
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strs_state <= strs_too_long ? ST_STRS_DROP : ST_STRS_HDR;
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end
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end
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// ST_STRS_DROP
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// ------------------
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ST_STRS_DROP: begin
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if (s_axis_strs_tvalid && s_axis_strs_tlast)
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strs_state <= ST_STRS_HDR;
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end
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default: begin
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// We should never get here
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strs_state <= ST_STRS_HDR;
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end
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endcase
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end
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end
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assign s_axis_strs_tready = (strs_state != ST_STRS_LATCH);
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assign msg_i_tvalid = (strs_state == ST_STRS_LATCH);
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assign msg_i_tdata = (chdr256_strs_get_src_epid(cached_strs_msg) != cached_dst_epid) ?
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CHDR_STRS_STATUS_CMDERR : chdr256_strs_get_status(cached_strs_msg);
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// ---------------------------------------------------
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// Main State Machine
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// ---------------------------------------------------
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localparam [2:0] ST_PASS_DATA = 3'd0; // Passing input axis_data out
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localparam [2:0] ST_STRC_HDR = 3'd1; // Sending CHDR header for stream cmd
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localparam [2:0] ST_STRC_W0 = 3'd2; // Sending first word of stream cmd
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localparam [2:0] ST_STRC_W1 = 3'd3; // Sending second word of stream cmd
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localparam [2:0] ST_STRC_WAIT = 3'd4; // Waiting for response (stream status)
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localparam [2:0] ST_INIT_DLY = 3'd5; // Finishing command execution
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reg [2:0] state = ST_PASS_DATA;
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reg mid_pkt = 1'b0;
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reg [15:0] data_seq_num = 16'd0;
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reg [15:0] strc_seq_num = 16'd0;
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reg [2:0] cfg_delay = 3'd0;
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reg cfg_fc_freq_bytes_nz;
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reg cfg_fc_freq_pkts_nz;
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always @(posedge clk) begin
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if (rst) begin
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state <= ST_PASS_DATA;
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mid_pkt <= 1'b0;
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data_seq_num <= 16'd0;
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strc_seq_num <= 16'd0;
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cfg_pending <= 1'b0;
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cfg_failed <= 1'b0;
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cfg_fc_freq_bytes_nz <= 1'bX;
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cfg_fc_freq_pkts_nz <= 1'bX;
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end else begin
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// Capture if the flow-control update frequency is 0 (never)
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cfg_fc_freq_bytes_nz <= (cfg_fc_freq_bytes != 0);
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cfg_fc_freq_pkts_nz <= (cfg_fc_freq_pkts != 0);
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case (state)
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// ST_PASS_DATA
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// ------------------
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// This is the default state where input data is passed to the
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// output port. Flow control is enforced in this state.
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// This state also serves as the launch state for a configuration
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// operation (using cfg_start)
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ST_PASS_DATA: begin
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// Update the mid_pkt flag and sequence number
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if (chdr_out_tvalid && chdr_out_tready) begin
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mid_pkt <= !chdr_out_tlast;
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if (chdr_out_tlast)
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data_seq_num <= data_seq_num + 16'd1;
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end
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// Launch a configuration operation
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if (cfg_start) begin
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// Latch cfg command
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cfg_pending <= 1'b1;
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cfg_failed <= 1'b0;
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// Disable flow control
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fc_enabled <= 1'b0;
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// Cache relevant data from the cfg cmd
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lossy_xport <= cfg_lossy_xport;
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cached_dst_epid <= cfg_dst_epid;
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headroom_bytes <= cfg_fc_headroom_bytes;
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headroom_pkts <= cfg_fc_headroom_pkts;
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end
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// Wait for current packet to transfer then begin the
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// configuration process or stream command
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if (cfg_start || cfg_pending || fc_resync_req) begin
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if (mid_pkt) begin
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if (chdr_out_tvalid && chdr_out_tready && chdr_out_tlast)
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state <= ST_STRC_HDR;
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end else begin
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if (!(chdr_out_tvalid && chdr_out_tready))
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state <= ST_STRC_HDR;
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end
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end
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end
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// ST_STRC_HDR
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// ------------------
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// Send the CHDR header for a stream command
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ST_STRC_HDR: begin
|
|
if (chdr_out_tvalid && chdr_out_tready) begin
|
|
state <= ST_STRC_W0;
|
|
// Update seqnum for the next packet
|
|
strc_seq_num <= strc_seq_num + 16'd1;
|
|
end
|
|
// Update byte count for stream command
|
|
strc_cnt_bytes <= send_cnt_bytes;
|
|
end
|
|
|
|
// ST_STRC_W0
|
|
// ------------------
|
|
// Send the first line of a stream command
|
|
ST_STRC_W0: begin
|
|
if (chdr_out_tvalid && chdr_out_tready)
|
|
if (CHDR_W < 128)
|
|
state <= ST_STRC_W1;
|
|
else
|
|
state <= fc_resync_req ? ST_PASS_DATA : ST_STRC_WAIT;
|
|
end
|
|
|
|
// ST_STRC_W1
|
|
// ------------------
|
|
// Send the second line of a stream command
|
|
ST_STRC_W1: begin
|
|
if (chdr_out_tvalid && chdr_out_tready)
|
|
state <= fc_resync_req ? ST_PASS_DATA : ST_STRC_WAIT;
|
|
end
|
|
|
|
// ST_STRC_WAIT
|
|
// ------------------
|
|
// Done sending stream command. Wait for a response
|
|
ST_STRC_WAIT: begin
|
|
// Wait for a new response to arrive
|
|
if (msg_o_tvalid) begin
|
|
if (msg_o_tdata == CHDR_STRS_STATUS_OKAY) begin
|
|
state <= ST_INIT_DLY;
|
|
cfg_delay <= 3'd4;
|
|
data_seq_num <= 16'd0;
|
|
strc_seq_num <= 16'd0;
|
|
// Only enable flow control if we're requesting periodic flow
|
|
// control updates.
|
|
fc_enabled <= cfg_fc_freq_bytes_nz || cfg_fc_freq_pkts_nz;
|
|
end else begin
|
|
state <= ST_PASS_DATA;
|
|
cfg_failed <= 1'b1;
|
|
cfg_pending <= 1'b0;
|
|
end
|
|
end
|
|
end
|
|
|
|
// ST_INIT_DLY
|
|
// ------------------
|
|
// Delay matching state for ok_shreg
|
|
ST_INIT_DLY: begin
|
|
if (cfg_delay == 3'd0) begin
|
|
state <= ST_PASS_DATA;
|
|
cfg_pending <= 1'b0;
|
|
end else begin
|
|
cfg_delay <= cfg_delay - 3'd1;
|
|
end
|
|
end
|
|
|
|
// We should never get here
|
|
default: begin
|
|
state <= ST_PASS_DATA;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
// Header for output CHDR data
|
|
wire [CHDR_W-1:0] data_header;
|
|
assign data_header[63:0] = chdr_set_seq_num(
|
|
chdr_set_dst_epid(s_axis_data_tdata[63:0], cached_dst_epid),
|
|
data_seq_num);
|
|
generate if (CHDR_W > 64)
|
|
assign data_header[CHDR_W-1:64] = s_axis_data_tdata[CHDR_W-1:64];
|
|
endgenerate
|
|
|
|
// Header for stream command
|
|
wire [CHDR_W-1:0] strc_header;
|
|
assign strc_header[63:0] = chdr_build_header(
|
|
/*VC*/ 6'd0, /*eob*/ 1'b0, /*eov*/ 1'b0, CHDR_PKT_TYPE_STRC, CHDR_NO_MDATA,
|
|
strc_seq_num, 16'd16+(CHDR_W/8), cached_dst_epid);
|
|
generate if (CHDR_W > 64)
|
|
assign strc_header[CHDR_W-1:64] = {(CHDR_W-64){1'b0}};
|
|
endgenerate
|
|
|
|
// Payload for stream command
|
|
wire [127:0] strc_init_payload = chdr128_strc_build(
|
|
{24'h0, cfg_fc_freq_bytes}, {16'h0, cfg_fc_freq_pkts},
|
|
/*op_data*/ 4'h0, CHDR_STRC_OPCODE_INIT, cfg_this_epid);
|
|
wire [127:0] strc_resync_payload = chdr128_strc_build(
|
|
strc_cnt_bytes, send_cnt_pkts,
|
|
/*op_data*/ 4'h0, CHDR_STRC_OPCODE_RESYNC, cfg_this_epid);
|
|
wire [127:0] strc_payload = fc_resync_req ? strc_resync_payload : strc_init_payload;
|
|
|
|
always @(*) begin
|
|
case (state)
|
|
ST_PASS_DATA: begin
|
|
chdr_out_tdata = mid_pkt ? s_axis_data_tdata : data_header;
|
|
chdr_out_tlast = s_axis_data_tlast;
|
|
chdr_out_tvalid = s_axis_data_tvalid && ok_to_send;
|
|
end
|
|
ST_STRC_HDR: begin
|
|
chdr_out_tdata = strc_header;
|
|
chdr_out_tlast = 1'b0;
|
|
chdr_out_tvalid = ok_to_send;
|
|
end
|
|
ST_STRC_W0: begin
|
|
chdr_out_tdata = strc_payload;
|
|
chdr_out_tlast = (CHDR_W < 128) ? 1'b0 : 1'b1;
|
|
chdr_out_tvalid = ok_to_send;
|
|
end
|
|
ST_STRC_W1: begin
|
|
// We will enter this state only if CHDR_W = 64
|
|
chdr_out_tdata = strc_payload[127:64];
|
|
chdr_out_tlast = 1'b1;
|
|
chdr_out_tvalid = ok_to_send;
|
|
end
|
|
default: begin
|
|
chdr_out_tdata = {CHDR_W{1'b0}};
|
|
chdr_out_tlast = 1'b0;
|
|
chdr_out_tvalid = 1'b0;
|
|
end
|
|
endcase
|
|
end
|
|
assign s_axis_data_tready = (state == ST_PASS_DATA) && chdr_out_tready && ok_to_send;
|
|
|
|
// Consume all messages when passing data forward. The flow control state is automatically
|
|
// updated outside the message FIFO. When a stream command is issued, we wait for the
|
|
// "wait" state to consume responses.
|
|
assign msg_o_tready = msg_o_tvalid && (state == ST_PASS_DATA || state == ST_STRC_WAIT);
|
|
|
|
// Acknowledge a flow control resync command
|
|
assign fc_resync_ack = fc_resync_req && (state == ST_STRC_W1 || state == ST_STRC_W0) &&
|
|
chdr_out_tvalid && chdr_out_tready && chdr_out_tlast;
|
|
|
|
// ---------------------------------------------------
|
|
// Stream Status Reporting
|
|
// ---------------------------------------------------
|
|
|
|
wire runtime_err_stb = msg_o_tvalid && msg_o_tready && (state == ST_PASS_DATA);
|
|
assign seq_err_stb = runtime_err_stb && (msg_o_tdata == CHDR_STRS_STATUS_SEQERR);
|
|
assign data_err_stb = runtime_err_stb && (msg_o_tdata == CHDR_STRS_STATUS_DATAERR);
|
|
assign route_err_stb = runtime_err_stb && (msg_o_tdata == CHDR_STRS_STATUS_RTERR);
|
|
|
|
always @(posedge clk) begin
|
|
if (rst || !fc_enabled) begin
|
|
seq_err_cnt <= 32'd0;
|
|
data_err_cnt <= 32'd0;
|
|
route_err_cnt <= 32'd0;
|
|
end else begin
|
|
if (seq_err_stb)
|
|
seq_err_cnt <= seq_err_cnt + 32'd1;
|
|
if (data_err_stb)
|
|
data_err_cnt <= data_err_cnt + 32'd1;
|
|
if (route_err_stb)
|
|
route_err_cnt <= route_err_cnt + 32'd1;
|
|
end
|
|
end
|
|
|
|
endmodule // chdr_stream_output
|