37 lines
1.5 KiB
Systemverilog
37 lines
1.5 KiB
Systemverilog
/*
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-------------------------------------------------------------------------------
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--
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-- File: LvFpga_Chinch_Interface.vh
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-- Author: Ashish Chaudhari
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-- Original Project: EttusUsrpB250Top
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-- Date: 1 Oct 2013
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--
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-------------------------------------------------------------------------------
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-- (c) 2013 Copyright National Instruments Corporation
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-- All Rights Reserved
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-- National Instruments Internal Information
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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-------------------------------------------------------------------------------
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*/
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//Physical link width for the IoPort2 interface to the STC3
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`define LVFPGA_IFACE_LINK_WIDTH 16
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//DMA Related Constants
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`define LVFPGA_IFACE_DMA_CHAN_WIDTH 64 //DMA data bus width
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`define LVFPGA_IFACE_DMA_SIZE_WIDTH 11 //DMA FIFO fullness count width
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`define LVFPGA_IFACE_NUM_RX_DMA_CNT 6 //Number of RX DMA channels
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`define LVFPGA_IFACE_NUM_TX_DMA_CNT 6 //Number of TX DMA channels
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`define LVFPGA_IFACE_RX_DMA_INDEX 0 //Index for the first RX DMA channel
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`define LVFPGA_IFACE_TX_DMA_INDEX 6 //Index for the first TX DMA channel
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//User register port constants
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`define LVFPGA_IFACE_UREG_ADDR_WIDTH 20 //Address width
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`define LVFPGA_IFACE_UREG_DATA_WIDTH 32 //Payload width
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`define LVFPGA_IFACE_UREG_SIZE_WIDTH 2 //Transaction size width
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//Chinch register port constants
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`define LVFPGA_IFACE_CREG_ADDR_WIDTH 32 //Address width
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`define LVFPGA_IFACE_CREG_DATA_WIDTH 64 //Payload width
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`define LVFPGA_IFACE_CREG_SIZE_WIDTH 2 //Transaction size width
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