110 lines
2.8 KiB
Verilog
110 lines
2.8 KiB
Verilog
//
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// Copyright 2018 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Description:
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// A module to monitor a an AXI-Stream link and gather various
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// metric about packets and the stream in general
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module axis_strm_monitor #(
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parameter WIDTH = 64,
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parameter COUNT_W = 32,
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parameter PKT_LENGTH_EN = 0,
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parameter PKT_CHKSUM_EN = 0,
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parameter PKT_COUNT_EN = 0,
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parameter XFER_COUNT_EN = 0
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)(
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// Clocks and resets
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input wire clk,
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input wire reset,
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// Stream to monitor
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input wire [WIDTH-1:0] axis_tdata,
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input wire axis_tlast,
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input wire axis_tvalid,
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input wire axis_tready,
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// Packet Stats
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output wire sop,
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output wire eop,
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output reg [15:0] pkt_length = 16'd0,
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output wire [WIDTH-1:0] pkt_chksum,
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// Stream Stats
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output reg [COUNT_W-1:0] pkt_count = {COUNT_W{1'b0}},
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output reg [COUNT_W-1:0] xfer_count = {COUNT_W{1'b0}}
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);
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//----------------------------
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// Packet specific
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//----------------------------
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reg pkt_head = 1'b1;
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wire xfer = axis_tvalid & axis_tready;
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assign sop = pkt_head & xfer;
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assign eop = xfer & axis_tlast;
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always @(posedge clk) begin
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if (reset) begin
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pkt_head <= 1'b1;
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end else begin
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if (pkt_head) begin
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if (xfer)
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pkt_head <= ~eop;
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end else begin
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if (eop)
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pkt_head <= 1'b0;
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end
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end
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end
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generate if (PKT_LENGTH_EN) begin
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// Count the number of lines (transfers) in a packet
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always @(posedge clk) begin
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if (reset | eop) begin
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pkt_length <= 16'd1;
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end else if (xfer) begin
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pkt_length <= pkt_length + 1'b1;
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end
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end
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end else begin
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// Default packet length is 0
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always @(*) pkt_length <= 16'd0;
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end endgenerate
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generate if (PKT_CHKSUM_EN) begin
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// Compute the XOR checksum of the lines in a packet
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reg [WIDTH-1:0] chksum_prev = {WIDTH{1'b0}};
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always @(posedge clk) begin
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if (reset) begin
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chksum_prev <= {WIDTH{1'b0}};
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end else if (xfer) begin
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chksum_prev <= pkt_chksum;
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end
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end
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assign pkt_chksum = chksum_prev ^ axis_tdata;
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end else begin
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// Default checksum is 0
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assign pkt_chksum = {WIDTH{1'b0}};
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end endgenerate
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//----------------------------
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// Stream specific
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//----------------------------
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always @(posedge clk) begin
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if (reset | (PKT_COUNT_EN == 0)) begin
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pkt_count <= {COUNT_W{1'b0}};
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end else if (eop) begin
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pkt_count <= pkt_count + 1'b1;
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end
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end
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always @(posedge clk) begin
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if (reset | (XFER_COUNT_EN == 0)) begin
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xfer_count <= {COUNT_W{1'b0}};
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end else if (xfer) begin
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xfer_count <= xfer_count + 1'b1;
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end
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end
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endmodule |