97 lines
1.9 KiB
Systemverilog
97 lines
1.9 KiB
Systemverilog
//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Interface: regport_if
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//
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// Description: RegPort interface for SystemVerilog.
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//
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interface regport_if #(
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int AWIDTH = 14,
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int DWIDTH = 32
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) (
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input logic clk,
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input logic rst = 1'b0
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);
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logic wr_req;
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logic [AWIDTH-1:0] wr_addr;
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logic [DWIDTH-1:0] wr_data;
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logic rd_req;
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logic [AWIDTH-1:0] rd_addr;
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logic rd_resp;
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logic [DWIDTH-1:0] rd_data;
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// View from the master side
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modport master (
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input clk,
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input rst,
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output wr_req,
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output wr_addr,
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output wr_data,
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output rd_req,
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output rd_addr,
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input rd_resp,
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input rd_data
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);
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// View from the slave side
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modport slave (
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input clk,
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input rst,
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input wr_req,
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input wr_addr,
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input wr_data,
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input rd_req,
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input rd_addr,
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output rd_resp,
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output rd_data
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);
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//---------------------------------------------------------------------------
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// Simulation Tasks
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//---------------------------------------------------------------------------
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//synthesis translate_off
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function automatic void init();
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wr_req <= 1'b0;
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wr_addr <= 'X;
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wr_data <= 'X;
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rd_req <= 1'b0;
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rd_addr <= 'X;
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endfunction : init
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task automatic write(bit [AWIDTH-1:0] addr, bit [DWIDTH-1:0] data);
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@(posedge clk);
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wr_req <= 1'b1;
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wr_addr <= addr;
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wr_data <= data;
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@(posedge clk);
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init();
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endtask : write
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task automatic read(bit [AWIDTH-1:0] addr, output bit [DWIDTH-1:0] data);
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@(posedge clk);
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rd_req <= 1'b1;
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rd_addr <= addr;
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forever begin
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@(posedge clk);
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rd_req <= 1'b0;
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rd_addr <= 'X;
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if (rd_resp) begin
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data = rd_data;
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break;
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end
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end
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init();
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endtask : read
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//synthesis translate_on
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endinterface : regport_if
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