167 lines
6.4 KiB
Systemverilog
167 lines
6.4 KiB
Systemverilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Header File: axi_lite.vh
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// Description: Macros for use with AXI4-Lite
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//
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//-----------------------------------------------------------------------------
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// AXI4-Lite
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//-----------------------------------------------------------------------------
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// Macro that drives o from i for all fields. Of course ready runs in the
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// counter direction.
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`define AXI4LITE_ASSIGN(O,I) \
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/* write address channel */\
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``O.awaddr = ``I.awaddr;\
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``O.awvalid = ``I.awvalid;\
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``I.awready = ``O.awready;\
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/* write data channel */\
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``O.wdata = ``I.wdata;\
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``O.wstrb = ``I.wstrb;\
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``O.wvalid = ``I.wvalid;\
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``I.wready = ``O.wready;\
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/* write resp channel */\
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``I.bresp = ``O.bresp;\
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``I.bvalid = ``O.bvalid;\
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``O.bready = ``I.bready;\
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/* read address channel */\
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``O.araddr = ``I.araddr;\
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``O.arvalid = ``I.arvalid;\
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``I.arready = ``O.arready;\
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/* read resp channel */\
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``I.rdata = ``O.rdata;\
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``I.rresp = ``O.rresp;\
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``I.rvalid = ``O.rvalid;\
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``O.rready = ``I.rready;
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// All signals
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`define AXI4LITE_PORT_ASSIGN(FORMAL,ACTUAL) \
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.``FORMAL``_aclk(``ACTUAL``.clk),\
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.``FORMAL``_sreset(``ACTUAL``.rst),\
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.``FORMAL``_araddr(``ACTUAL``.araddr),\
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.``FORMAL``_arready(``ACTUAL``.arready),\
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.``FORMAL``_arvalid(``ACTUAL``.arvalid),\
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.``FORMAL``_awaddr(``ACTUAL``.awaddr),\
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.``FORMAL``_awready(``ACTUAL``.awready),\
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.``FORMAL``_awvalid(``ACTUAL``.awvalid),\
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.``FORMAL``_bready(``ACTUAL``.bready),\
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.``FORMAL``_bresp(``ACTUAL``.bresp[1:0]),\
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.``FORMAL``_bvalid(``ACTUAL``.bvalid),\
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.``FORMAL``_rdata(``ACTUAL``.rdata),\
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.``FORMAL``_rready(``ACTUAL``.rready),\
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.``FORMAL``_rresp(``ACTUAL``.rresp[1:0]),\
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.``FORMAL``_rvalid(``ACTUAL``.rvalid),\
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.``FORMAL``_wdata(``ACTUAL``.wdata),\
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.``FORMAL``_wready(``ACTUAL``.wready),\
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.``FORMAL``_wstrb(``ACTUAL``.wstrb),\
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.``FORMAL``_wvalid(``ACTUAL``.wvalid),
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//NR removes clock and reset
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`define AXI4LITE_PORT_ASSIGN_NR(FORMAL,ACTUAL) \
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.``FORMAL``_araddr(``ACTUAL``.araddr),\
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.``FORMAL``_arready(``ACTUAL``.arready),\
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.``FORMAL``_arvalid(``ACTUAL``.arvalid),\
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.``FORMAL``_awaddr(``ACTUAL``.awaddr),\
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.``FORMAL``_awready(``ACTUAL``.awready),\
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.``FORMAL``_awvalid(``ACTUAL``.awvalid),\
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.``FORMAL``_bready(``ACTUAL``.bready),\
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.``FORMAL``_bresp(``ACTUAL``.bresp[1:0]),\
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.``FORMAL``_bvalid(``ACTUAL``.bvalid),\
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.``FORMAL``_rdata(``ACTUAL``.rdata),\
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.``FORMAL``_rready(``ACTUAL``.rready),\
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.``FORMAL``_rresp(``ACTUAL``.rresp[1:0]),\
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.``FORMAL``_rvalid(``ACTUAL``.rvalid),\
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.``FORMAL``_wdata(``ACTUAL``.wdata),\
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.``FORMAL``_wready(``ACTUAL``.wready),\
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.``FORMAL``_wstrb(``ACTUAL``.wstrb),\
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.``FORMAL``_wvalid(``ACTUAL``.wvalid),
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//NRS removes wstrb clock and reset
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`define AXI4LITE_PORT_ASSIGN_NRS(FORMAL,ACTUAL) \
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.``FORMAL``_araddr(``ACTUAL``.araddr),\
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.``FORMAL``_arready(``ACTUAL``.arready),\
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.``FORMAL``_arvalid(``ACTUAL``.arvalid),\
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.``FORMAL``_awaddr(``ACTUAL``.awaddr),\
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.``FORMAL``_awready(``ACTUAL``.awready),\
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.``FORMAL``_awvalid(``ACTUAL``.awvalid),\
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.``FORMAL``_bready(``ACTUAL``.bready),\
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.``FORMAL``_bresp(``ACTUAL``.bresp[1:0]),\
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.``FORMAL``_bvalid(``ACTUAL``.bvalid),\
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.``FORMAL``_rdata(``ACTUAL``.rdata),\
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.``FORMAL``_rready(``ACTUAL``.rready),\
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.``FORMAL``_rresp(``ACTUAL``.rresp[1:0]),\
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.``FORMAL``_rvalid(``ACTUAL``.rvalid),\
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.``FORMAL``_wdata(``ACTUAL``.wdata),\
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.``FORMAL``_wready(``ACTUAL``.wready),\
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.``FORMAL``_wvalid(``ACTUAL``.wvalid),
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`define AXI4LITE_DEBUG_ASSIGN(O,I) \
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(* mark_debug = "true" *) logic [``I.ADDR_WIDTH-1:0] ``I``_debug_awaddr;\
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(* mark_debug = "true" *) logic ``I``_debug_awvalid;\
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(* mark_debug = "true" *) logic ``I``_debug_awready;\
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(* mark_debug = "true" *) logic [``I.DATA_WIDTH-1:0] ``I``_debug_wdata;\
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(* mark_debug = "true" *) logic [``I.BYTES_PER_WORD-1:0] ``I``_debug_wstrb;\
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(* mark_debug = "true" *) logic ``I``_debug_wvalid;\
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(* mark_debug = "true" *) logic ``I``_debug_wready;\
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(* mark_debug = "true" *) logic [1:0] ``I``_debug_bresp;\
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(* mark_debug = "true" *) logic ``I``_debug_bvalid;\
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(* mark_debug = "true" *) logic ``I``_debug_bready;\
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(* mark_debug = "true" *) logic [``I.ADDR_WIDTH-1:0] ``I``_debug_araddr;\
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(* mark_debug = "true" *) logic ``I``_debug_arvalid;\
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(* mark_debug = "true" *) logic ``I``_debug_arready;\
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(* mark_debug = "true" *) logic [``I.DATA_WIDTH-1:0] ``I``_debug_rdata;\
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(* mark_debug = "true" *) logic [1:0] ``I``_debug_rresp;\
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(* mark_debug = "true" *) logic ``I``_debug_rvalid;\
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(* mark_debug = "true" *) logic ``I``_debug_rready;\
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always_comb begin\
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/* write address channel */\
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``I``_debug_awaddr = ``I.awaddr;\
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``I``_debug_awvalid = ``I.awvalid;\
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``I.awready = ``I``_debug_awready;\
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/* write data channel */\
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``I``_debug_wdata = ``I.wdata;\
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``I``_debug_wstrb = ``I.wstrb;\
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``I``_debug_wvalid = ``I.wvalid;\
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``I.wready = ``I``_debug_wready;\
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/* write resp channel */\
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``I.bresp = ``I``_debug_bresp;\
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``I.bvalid = ``I``_debug_bvalid;\
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``I``_debug_bready = ``I.bready;\
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/* read address channel */\
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``I``_debug_araddr = ``I.araddr;\
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``I``_debug_arvalid = ``I.arvalid;\
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``I.arready = ``I``_debug_arready;\
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/* read resp channel */\
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``I.rdata = ``I``_debug_rdata;\
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``I.rresp = ``I``_debug_rresp;\
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``I.rvalid = ``I``_debug_rvalid;\
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``I``_debug_rready = ``I.rready;\
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end\
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always_comb begin\
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/* write address channel */\
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``O.awaddr = ``I``_debug_awaddr;\
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``O.awvalid = ``I``_debug_awvalid;\
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``I``_debug_awready = ``O.awready;\
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/* write data channel */\
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``O.wdata = ``I``_debug_wdata;\
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``O.wstrb = ``I``_debug_wstrb;\
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``O.wvalid = ``I``_debug_wvalid;\
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``I``_debug_wready = ``O.wready;\
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/* write resp channel */\
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``I``_debug_bresp = ``O.bresp;\
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``I``_debug_bvalid = ``O.bvalid;\
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``O.bready = ``I``_debug_bready;\
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/* read address channel */\
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``O.araddr = ``I``_debug_araddr;\
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``O.arvalid = ``I``_debug_arvalid;\
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``I``_debug_arready = ``O.arready;\
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/* read resp channel */\
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``I``_debug_rdata = ``O.rdata;\
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``I``_debug_rresp = ``O.rresp;\
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``I``_debug_rvalid = ``O.rvalid;\
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``O.rready = ``I``_debug_rready;\
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end
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