Andrew Moch
e008853357
(1) Synthesizable AxiLiteIf
(2) Simulation model for AxiLite contains an AxiLiteTransaction class
and an AxiLiteBfm class.
Important Methods
a. wr - performs non-blocking write and checks for expected response
b. wr_block - performs a blocking write and provides response
c. rd - performs a non-blocking read and checks for expected response
d. rd_block - persforms a blocking read and provides response
The model allows parallel execution of reads and writes, but enforces
rd and write ordering when using the above methods. When transactions
are posted directly, ordering is not guaranteed, and reads and writes
are put on the interface immediately.
Original-commit: afee1888dd7c2d9d95e537f505ce7ab36252763a
22 lines
691 B
Systemverilog
22 lines
691 B
Systemverilog
//
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// Copyright 2020 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Package: PkgAxiLite
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// Description:
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// AXI4-Lite is an ARM standard for lighter weight registers
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// axis based on the AXI4 protocol. For more information
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// on the spec see - https://developer.arm.com/docs/ihi0022/d
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//
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// This package contains types used for AxiLiteIf.
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//
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//-----------------------------------------------------------------------------
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// AXI4-Lite Package
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//-----------------------------------------------------------------------------
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package PkgAxiLite;
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typedef enum logic [1:0] {OKAY=0,SLVERR=2,DECERR=3} resp_t;
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endpackage : PkgAxiLite
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