Files
Wade Fife bb2bfbfe95 fpga: lib: Add AXI-Stream load split and merge modules
Original-commit: 32fb626ef1b1d3078fd331143b03cd38d1e155f0
2025-02-14 15:59:19 -06:00

45 lines
997 B
Makefile

#
# Copyright 2012-2013 Ettus Research LLC
# Copyright 2014 Ettus Research, a National Instruments Company
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
##################################################
# FIFO Sources
##################################################
AXI_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/axi/, \
axi_chdr_header_trigger.v \
axi_chdr_test_pattern.v \
axi_defs.v \
axi_dma_fifo.v \
axi_dma_master.v \
axi_embed_tlast.v \
axi_extract_tlast.v \
axi_fast_extract_tlast.v \
axi_embed_tlast_tkeep.v \
axi_extract_tlast_tkeep.v \
axi_fast_fifo.v \
axi_to_strobed.v \
axis_data_swap.v \
axi_dummy.v \
strobed_to_axi.v \
axi_add_preamble.v \
axi_strip_preamble.v \
crc_xnor.v \
axis_packet_flush.v \
axis_shift_register.v \
axis_upsizer.v \
axis_downsizer.v \
axis_width_conv.v \
axis_split.v \
axis_split_bus.v \
axis_combine.v \
axis_load_split.sv \
axis_load_merge.sv \
axis_packetize.v \
axis_pkt_throttle.sv \
axis_data_if_packetize.v \
axis_sideband_tuser.v \
))