71 lines
1.8 KiB
Makefile
71 lines
1.8 KiB
Makefile
#
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# Copyright 2015 Ettus Research LLC
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#
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_design_builder.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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ifndef PRODUCT
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PRODUCT=X310
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endif
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ARCH=$(XIL_ARCH_${PRODUCT})
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PART_ID=$(XIL_PART_ID_${PRODUCT})
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# Include makefiles and sources for the DUT and its dependencies
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include $(LIB_DIR)/control/Makefile.srcs
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include $(LIB_DIR)/fifo/Makefile.srcs
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include $(LIB_DIR)/timing/Makefile.srcs
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include $(LIB_DIR)/packet_proc/Makefile.srcs
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include $(LIB_DIR)/vita/Makefile.srcs
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include $(LIB_DIR)/dsp/Makefile.srcs
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include $(LIB_DIR)/axi/Makefile.srcs
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include $(LIB_DIR)/radio/Makefile.srcs
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include $(BASE_DIR)/x300/coregen_dsp/Makefile.srcs
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DESIGN_SRCS = $(abspath \
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$(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) \
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$(TIMING_SRCS) \
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$(PACKET_PROC_SRCS) \
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$(VITA_SRCS) \
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$(DSP_SRCS) \
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$(AXI_SRCS) \
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$(RADIO_SRCS) \
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$(COREGEN_DSP_SRCS) \
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)
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TOP_MODULE = radio
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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IP_DIR = $(BASE_DIR)/x300/ip
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# Include makefiles and sources for all IP components
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# *after* defining the IP_DIR
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include $(IP_DIR)/fifo_short_2clk/Makefile.inc
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include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
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DESIGN_SRCS += $(abspath \
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$(IP_FIFO_4K_2CLK_SRCS) \
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$(IP_FIFO_SHORT_2CLK_SRCS) \
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)
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# DESIGN_SRCS and VERILOG_DEFS must be defined
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.DEFAULT_GOAL := netlist
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netlist: .prereqs $(DESIGN_SRCS)
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$(call BUILD_VIVADO_DESIGN,$(abspath ./build.tcl),$(TOP_MODULE),$(PART_ID))
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clean:
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@rm -rf build
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@rm -rf build-ip
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.PHONY: netlist clean |