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#
# Xilinx Core Generator version 14.4
# Date: Thu Jan 17 18:44:40 2013
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
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#
#  Generated from component: xilinx.com:ip:mig_7series:1.8
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT MIG_7_Series family Xilinx,_Inc. 1.8
# END Select
# BEGIN Parameters
CSET component_name=ddr3_interface_fast
CSET xml_input_file=./ddr3_interface_fast/mig.prj
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T05:23:34Z
# END Extra information
GENERATE
# CRC: 84a5b072