xilinx.com xci unknown 1.0 misc_clock_gen false 100000000 false 100000000 false 100000000 false 100000000 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 1 LEVEL_HIGH 100000000 0 0 0.0 0 0 100000000 0 0 0.0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.0 AXI4LITE READ_WRITE 0 0 0 0 0 0 MMCM cddcdone cddcreq 0000 0000 clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 59.989999999999995 100.0 0000 0000 198.41270 0000 0000 303.81945 BUFGCE 50.0 false 198.41270 0.000 50.0 198.412704761 0.000 1 0000 0000 100.000 BUFGCE 50.0 false 303.81945 0.000 50.0 305.55555 0.000 1 1 0000 0000 100.000 BUFGCE 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFGCE 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFGCE 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFGCE 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 BUFGCE 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 VCO clk_in_sel meas_clk ddr3_dma_clk clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 CLK_VALID NA daddr dclk den din 0000 1 0.6530612244897959 0.16326530612244897 0.16326530612244897 0.16326530612244897 0.16326530612244897 0.16326530612244897 dout drdy dwe 93.000 1.000 0 0 0 0 0 0 0 0 FDBK_AUTO 0000 0000 0 Input Clock Freq (MHz) Input Jitter (UI) __primary________166.666667____________0.010 no_secondary_input_clock input_clk_stopped 0 Units_MHz No_Jitter locked 0000 0000 0000 false false false false false false false false OPTIMIZED 21.875 0.000 FALSE 6.000 10.000 6.125 0.500 0.000 FALSE 4 0.500 0.000 FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE ZHOLD 3 None 0.010 0.010 FALSE 64.000 2.000 2 0 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) meas_clk__198.41270______0.000______50.0______113.755____141.292 ddr3_dma_clk__303.81945______0.000______50.0______105.705____141.292 no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output 0 0 128.000 1.000 WAVEFORM UNKNOWN false false false false false OPTIMIZED 1 0.000 1.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 No notes 0.010 power_down 0000 1 clk_in MMCM AUTO 166.666667 0.010 10.000 No_buffer psclk psdone psen psincdec 100.0 0 reset 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 4000 0.004 STATUS 11 32 100.0 100.0 100.0 100.0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1440.000 600.000 misc_clock_gen MMCM false empty cddcdone cddcreq clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 59.989999999999995 0.010 100.0 0.010 BUFGCE 113.755 false 141.292 50.0 198.412704761 0.000 1 true BUFGCE 105.705 false 141.292 50.0 305.55555 0.000 1 true BUFGCE 81.390 false 326.622 50.000 100.000 0.000 1 false BUFGCE 81.390 false 326.622 50.000 100.000 0.000 1 false BUFGCE 0.0 false 0.0 50.000 100.000 0.000 1 false BUFGCE 0.0 false 0.0 50.000 100.000 0.000 1 false BUFGCE 0.0 false 0.0 50.000 100.000 0.000 1 false 600.000 Custom Custom clk_in_sel meas_clk false ddr3_dma_clk false clk_out3 false clk_out4 false clk_out5 false clk_out6 false clk_out7 false CLK_VALID auto misc_clock_gen daddr dclk den Custom Custom din dout drdy dwe false false false false false false false false false FDBK_AUTO input_clk_stopped frequency Enable_AXI Units_MHz Units_UI UI No_Jitter locked OPTIMIZED 21.875 0.000 false 6.000 10.000 6.125 0.500 0.000 false 4 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false ZHOLD 3 None 0.010 0.010 false 2 false false false WAVEFORM false UNKNOWN OPTIMIZED 4 0.000 10.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 None 0.010 power_down 1 clk_in MMCM mmcm_adv 166.666667 0.010 10.000 No_buffer psclk psdone psen psincdec 100.0 REL_PRIMARY Custom reset ACTIVE_HIGH 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 250 0.004 STATUS empty 100.0 100.0 100.0 100.0 false false false false false false false true false false true false false false false false true true false false zynq xc7z100 ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 8 TRUE . . 2021.1 OUT_OF_CONTEXT