# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args         # Identifier for the schema used to validate this file
copyright: >-                           # Copyright information used in file headers
  Copyright 2023 Ettus Research, a National Instruments Brand
license: >-                             # License information used in file headers
  SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0'                          # File version
chdr_width: 64                          # Bit width of the CHDR bus for this image
device: 'e320'
default_target: 'E320_1G'               # Target. This controls which transports are instantiated.
image_core_name: 'usrp_e320_fpga_1G'    # Name to use for the generated output files.
                                        # Change image_core_name and default_target in tandem,
                                        # because we won't generate the correct DTS files otherwise.

# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
  ep0:                                  # Stream endpoint name
    ctrl: True                          # Endpoint passes control traffic
    data: True                          # Endpoint passes data traffic
    buff_size: 32768                    # Ingress buffer size for data
  ep1:
    ctrl: False
    data: True
    buff_size: 32768
  ep2:
    ctrl: False
    data: True
    buff_size: 8192
  ep3:
    ctrl: False
    data: True
    buff_size: 8192

# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
  duc0:                                 # NoC block name
    block_desc: 'duc.yml'               # Block device descriptor file
    parameters:
      NUM_PORTS: 2
  ddc0:
    block_desc: 'ddc.yml'
    parameters:
      NUM_PORTS: 2
  radio0:
    block_desc: 'radio.yml'
    parameters:
      NUM_PORTS: 2
  fifo0:
    block_desc: 'axi_ram_fifo.yml'
    parameters:
      NUM_PORTS: 2
      # These parameters correspond to the memory interface on the E320
      MEM_ADDR_W:   31
      MEM_DATA_W:   64
      MEM_CLK_RATE: "300e6"
      # Create two non-overlapping 32 MB buffers by default
      FIFO_ADDR_BASE: "{31'h02000000, 31'h00000000}"
      FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF}"

# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
#   - srcblk  = Source block to connect
#   - srcport = Port on the source block to connect
#   - dstblk  = Destination block to connect
#   - dstport = Port on the destination block to connect
connections:
  # RF A TX
  - { srcblk: ep0,    srcport: out0,  dstblk: duc0,   dstport: in_0 }
  - { srcblk: duc0,   srcport: out_0, dstblk: radio0, dstport: in_0 }
  # RF A RX
  - { srcblk: radio0, srcport: out_0, dstblk: ddc0,   dstport: in_0 }
  - { srcblk: ddc0,   srcport: out_0, dstblk: ep0,    dstport: in0  }
  # RF B TX
  - { srcblk: ep1,    srcport: out0,  dstblk: duc0,   dstport: in_1 }
  - { srcblk: duc0,   srcport: out_1, dstblk: radio0, dstport: in_1 }
  # RF B RX
  - { srcblk: radio0, srcport: out_1, dstblk: ddc0,   dstport: in_1 }
  - { srcblk: ddc0,   srcport: out_1, dstblk: ep1,    dstport: in0  }
  #
  # DRAM FIFO Connections
  - { srcblk: ep2,    srcport: out0,  dstblk: fifo0,  dstport: in_0 }
  - { srcblk: fifo0,  srcport: out_0, dstblk: ep2,    dstport: in0  }
  - { srcblk: ep3,    srcport: out0,  dstblk: fifo0,  dstport: in_1 }
  - { srcblk: fifo0,  srcport: out_1, dstblk: ep3,    dstport: in0  }
  #
  # BSP Connections
  - { srcblk: radio0,   srcport: ctrlport, dstblk: _device_, dstport: ctrlport }
  - { srcblk: fifo0,    srcport: axi_ram,  dstblk: _device_, dstport: dram     }
  - { srcblk: _device_, srcport: radio,    dstblk: radio0,   dstport: radio    }
  - { srcblk: _device_, srcport: time,     dstblk: radio0,   dstport: time     }

# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
#   - srcblk  = Source block to connect (Always "_device"_)
#   - srcport = Clock domain on the source block to connect
#   - dstblk  = Destination block to connect
#   - dstport = Clock domain on the destination block to connect
clk_domains:
  - { srcblk: _device_, srcport: radio,      dstblk: radio0, dstport: radio }
  - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0,   dstport: ce    }
  - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0,   dstport: ce    }
  - { srcblk: _device_, srcport: dram,       dstblk: fifo0,  dstport: mem   }