xilinx.com xci unknown 1.0 xge_pcs_pma 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 100000000 0 0 0.0 0 0 0 0 0 0 0 0 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 0 0 0 0 0 0 0.0 false 100000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef false 0 0 0 0 undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 0 100000000 0 0 0.0 100000000 0 0 0.0 0 0 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0 0 0 0 0 0 156250000 undef 0.0 156250000 undef 0.0 156250000 undef 0.0 156250000 undef 0.0 0 0 0 0 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.0 AXI4LITE READ_WRITE 0 0 0 0 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.0 AXI4LITE READ_WRITE 0 0 0 0 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.0 AXI4LITE READ_WRITE 0 0 0 0 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.0 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 0 0 0 0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0 0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0.0 0 0 0 0 0 0 0 0 0 0 0 0 1 100 64 7 BASE-R Asynchronous CMACE4_X0Y0 Ethernet PCS/PMA 64-bit MII 0 0 1 0 0 0 0 0 0 zynquplus 0 NA 4 100.00 Quad X0Y0 1 156.25 GTY None 0 0 0 0 0 0 0 30 X0Y16 NA NA NA 10 8 64 1 0 2 0 AUTO 0 0 4000 0 4 1 0 0 1 100 BASE-R Asynchronous CMACE4_X0Y0 Ethernet PCS/PMA 64-bit xge_pcs_pma MII Custom 0 0 1 0 0 0 0 0 0 Custom 0 NA 100.00 Quad_X0Y4 1 156.25 GTY None 0 0 0 0 0 0 0 30 X0Y16 NA NA NA 10 1 0 2 0 AUTO 0 0 4000 0 false 1 zynquplusRFSOC xczu28dr ffvg1517 VERILOG MIXED -1 E TRUE TRUE IP_Flow 0 TRUE . . 2021.1 OUT_OF_CONTEXT