xilinx.com xci unknown 1.0 axi_eth_dma 0 0 1 0 32 0 0 0 64 100000000 1 1 1 0 1 0 0 1 1 0 0 256 1 2 1 0.000 AXI4 READ_WRITE 0 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 100000000 1 1 1 0 0 undef 0.000 8 0 0 0 32 0 0 0 64 100000000 0 0 0 0 0 0 0 1 0 0 0 256 1 2 1 0.000 AXI4 READ_ONLY 0 0 0 0 100000000 0 0.000 32 0 0 0 64 100000000 1 0 0 0 0 0 0 0 1 0 0 256 2 1 1 0.000 AXI4 WRITE_ONLY 0 0 0 0 100000000 0 0.000 32 0 0 0 32 100000000 1 1 1 0 1 0 0 1 1 0 0 1 1 0.000 AXI4 READ_WRITE 0 0 0 0 100000000 0 0.000 1 0 0 100000000 1 1 1 0 0 undef 0.000 8 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 10 0 0 0 32 100000000 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0.000 125 0 zynq 1 1 1 1 1 1 1 0 0 16 32 64 32 64 32 64 32 1 1 0 16 0 23 0 32 64 axi_eth_dma 32 125 0 1 1 1 1 1 1 1 0 64 64 64 0 16 1 1 0 16 64 0 23 0 0 zynq xc7z100 ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 20 TRUE . . 2019.1 OUT_OF_CONTEXT