xilinx.com xci unknown 1.0 input_sample_fifo 100000000 0 0.000 100000000 0 0.000 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 100000000 0 0.000 100000000 0 0.000 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 100000000 0 0.000 0 0 0 0 0 0 0 1 1 1 1 1 4 0 32 1 1 1 64 1 8 1 1 1 1 0 0 4 BlankString 28 1 32 64 1 64 2 0 28 0 1 0 0 0 0 0 0 0 0 kintex7 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 1 1 1 1 1 1 0 0 2 BlankString 1 0 0 0 0 1 512x36 1kx18 512x36 1kx36 512x36 1kx36 512x36 4 1022 1022 1022 1022 1022 1022 5 0 0 0 0 0 0 0 15 1023 1023 1023 1023 1023 1023 14 0 0 0 0 0 0 0 0 0 4 16 1 4 0 0 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 16 1024 16 1024 16 1024 16 1 4 10 4 10 4 10 4 1 32 0 0 false true false 0 0 Slave_Interface_Clock_Enable Common_Clock input_sample_fifo 64 false 4 false false 0 4 1022 1022 1022 1022 1022 1022 5 false false false false false false false false false Hard_ECC false false false false false false true false false true Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Independent_Clocks_Distributed_RAM 1 15 1023 1023 1023 1023 1023 1023 14 false false false 0 Native false false false false false false false false false false false false false false 28 16 1024 16 1024 16 1024 16 false 28 16 Embedded_Reg false false Active_High Active_High AXI4 First_Word_Fall_Through No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold READ_WRITE 0 1 false 4 Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered true Asynchronous_Reset false 0 0 0 0 0 4 false false Active_High Active_High true false false false false Active_High 0 false Active_High 1 false 4 false FIFO false false false false FIFO FIFO 2 2 false FIFO FIFO FIFO kintex7 xc7k410t ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 4 TRUE . . 2019.1 OUT_OF_CONTEXT