// // Copyright 2019 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // // Module: rfnoc_image_core (for x300) // This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) // Re-running that tool will overwrite this file! // File generated on: 2019-11-14T12:14:56.022475 // Source: ./x310_rfnoc_image_core.yml // Source SHA256: 41b259b31e2a09272ffb146ef99afe1672a44c86dd51104fa4d1821ad24d5518 module rfnoc_image_core #( parameter [15:0] PROTOVER = {8'd1, 8'd0} )( // Clocks input wire chdr_aclk, input wire ctrl_aclk, input wire core_arst, input wire radio_clk, input wire ce_clk, input wire dram_clk, // Basic input wire [15:0] device_id, //// IO ports ////////////////////////////////// // ctrlport_radio0 output wire [ 1-1:0] m_ctrlport_radio0_req_wr, output wire [ 1-1:0] m_ctrlport_radio0_req_rd, output wire [ 20-1:0] m_ctrlport_radio0_req_addr, output wire [ 32-1:0] m_ctrlport_radio0_req_data, output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, output wire [ 64-1:0] m_ctrlport_radio0_req_time, input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, input wire [ 2-1:0] m_ctrlport_radio0_resp_status, input wire [ 32-1:0] m_ctrlport_radio0_resp_data, // ctrlport_radio1 output wire [ 1-1:0] m_ctrlport_radio1_req_wr, output wire [ 1-1:0] m_ctrlport_radio1_req_rd, output wire [ 20-1:0] m_ctrlport_radio1_req_addr, output wire [ 32-1:0] m_ctrlport_radio1_req_data, output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, output wire [ 64-1:0] m_ctrlport_radio1_req_time, input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, input wire [ 2-1:0] m_ctrlport_radio1_resp_status, input wire [ 32-1:0] m_ctrlport_radio1_resp_data, // time_keeper input wire [ 64-1:0] radio_time, // x300_radio0 input wire [ 64-1:0] radio_rx_data_radio0, input wire [ 2-1:0] radio_rx_stb_radio0, output wire [ 2-1:0] radio_rx_running_radio0, output wire [ 64-1:0] radio_tx_data_radio0, input wire [ 2-1:0] radio_tx_stb_radio0, output wire [ 2-1:0] radio_tx_running_radio0, // x300_radio1 input wire [ 64-1:0] radio_rx_data_radio1, input wire [ 2-1:0] radio_rx_stb_radio1, output wire [ 2-1:0] radio_rx_running_radio1, output wire [ 64-1:0] radio_tx_data_radio1, input wire [ 2-1:0] radio_tx_stb_radio1, output wire [ 2-1:0] radio_tx_running_radio1, // dram input wire [ 1-1:0] axi_rst, output wire [ 2-1:0] m_axi_awid, output wire [ 64-1:0] m_axi_awaddr, output wire [ 16-1:0] m_axi_awlen, output wire [ 6-1:0] m_axi_awsize, output wire [ 4-1:0] m_axi_awburst, output wire [ 2-1:0] m_axi_awlock, output wire [ 8-1:0] m_axi_awcache, output wire [ 6-1:0] m_axi_awprot, output wire [ 8-1:0] m_axi_awqos, output wire [ 8-1:0] m_axi_awregion, output wire [ 2-1:0] m_axi_awuser, output wire [ 2-1:0] m_axi_awvalid, input wire [ 2-1:0] m_axi_awready, output wire [128-1:0] m_axi_wdata, output wire [ 16-1:0] m_axi_wstrb, output wire [ 2-1:0] m_axi_wlast, output wire [ 2-1:0] m_axi_wuser, output wire [ 2-1:0] m_axi_wvalid, input wire [ 2-1:0] m_axi_wready, input wire [ 2-1:0] m_axi_bid, input wire [ 4-1:0] m_axi_bresp, input wire [ 2-1:0] m_axi_buser, input wire [ 2-1:0] m_axi_bvalid, output wire [ 2-1:0] m_axi_bready, output wire [ 2-1:0] m_axi_arid, output wire [ 64-1:0] m_axi_araddr, output wire [ 16-1:0] m_axi_arlen, output wire [ 6-1:0] m_axi_arsize, output wire [ 4-1:0] m_axi_arburst, output wire [ 2-1:0] m_axi_arlock, output wire [ 8-1:0] m_axi_arcache, output wire [ 6-1:0] m_axi_arprot, output wire [ 8-1:0] m_axi_arqos, output wire [ 8-1:0] m_axi_arregion, output wire [ 2-1:0] m_axi_aruser, output wire [ 2-1:0] m_axi_arvalid, input wire [ 2-1:0] m_axi_arready, input wire [ 2-1:0] m_axi_rid, input wire [128-1:0] m_axi_rdata, input wire [ 4-1:0] m_axi_rresp, input wire [ 2-1:0] m_axi_rlast, input wire [ 2-1:0] m_axi_ruser, input wire [ 2-1:0] m_axi_rvalid, output wire [ 2-1:0] m_axi_rready, // Transport 0 (eth0 10G) input wire [64-1:0] s_eth0_tdata, input wire s_eth0_tlast, input wire s_eth0_tvalid, output wire s_eth0_tready, output wire [64-1:0] m_eth0_tdata, output wire m_eth0_tlast, output wire m_eth0_tvalid, input wire m_eth0_tready, // Transport 1 (eth1 1G) input wire [64-1:0] s_eth1_tdata, input wire s_eth1_tlast, input wire s_eth1_tvalid, output wire s_eth1_tready, output wire [64-1:0] m_eth1_tdata, output wire m_eth1_tlast, output wire m_eth1_tvalid, input wire m_eth1_tready, // Transport 2 (pcie PCIe) input wire [64-1:0] s_pcie_tdata, input wire s_pcie_tlast, input wire s_pcie_tvalid, output wire s_pcie_tready, output wire [64-1:0] m_pcie_tdata, output wire m_pcie_tlast, output wire m_pcie_tvalid, input wire m_pcie_tready ); localparam CHDR_W = 64; localparam MTU = 10; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; // ---------------------------------------------------- // CHDR Crossbar // ---------------------------------------------------- wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire xb_to_ep0_tlast ; wire xb_to_ep0_tvalid; wire xb_to_ep0_tready; wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire ep0_to_xb_tlast ; wire ep0_to_xb_tvalid; wire ep0_to_xb_tready; wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire xb_to_ep1_tlast ; wire xb_to_ep1_tvalid; wire xb_to_ep1_tready; wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire ep1_to_xb_tlast ; wire ep1_to_xb_tvalid; wire ep1_to_xb_tready; wire [CHDR_W-1:0] xb_to_ep2_tdata ; wire xb_to_ep2_tlast ; wire xb_to_ep2_tvalid; wire xb_to_ep2_tready; wire [CHDR_W-1:0] ep2_to_xb_tdata ; wire ep2_to_xb_tlast ; wire ep2_to_xb_tvalid; wire ep2_to_xb_tready; wire [CHDR_W-1:0] xb_to_ep3_tdata ; wire xb_to_ep3_tlast ; wire xb_to_ep3_tvalid; wire xb_to_ep3_tready; wire [CHDR_W-1:0] ep3_to_xb_tdata ; wire ep3_to_xb_tlast ; wire ep3_to_xb_tvalid; wire ep3_to_xb_tready; chdr_crossbar_nxn #( .CHDR_W (CHDR_W), .NPORTS (7), .DEFAULT_PORT (0), .MTU (MTU), .ROUTE_TBL_SIZE (6), .MUX_ALLOC ("ROUND-ROBIN"), .OPTIMIZE ("AREA"), .NPORTS_MGMT (3), .EXT_RTCFG_PORT (0), .PROTOVER (PROTOVER) ) chdr_xb_i ( .clk (rfnoc_chdr_clk), .reset (rfnoc_chdr_rst), .device_id (device_id), .s_axis_tdata ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_pcie_tdata, s_eth1_tdata, s_eth0_tdata}), .s_axis_tlast ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_pcie_tlast, s_eth1_tlast, s_eth0_tlast}), .s_axis_tvalid ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_pcie_tvalid, s_eth1_tvalid, s_eth0_tvalid}), .s_axis_tready ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_pcie_tready, s_eth1_tready, s_eth0_tready}), .m_axis_tdata ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_pcie_tdata, m_eth1_tdata, m_eth0_tdata}), .m_axis_tlast ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_pcie_tlast, m_eth1_tlast, m_eth0_tlast}), .m_axis_tvalid ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_pcie_tvalid, m_eth1_tvalid, m_eth0_tvalid}), .m_axis_tready ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_pcie_tready, m_eth1_tready, m_eth0_tready}), .ext_rtcfg_stb (1'h0), .ext_rtcfg_addr (16'h0), .ext_rtcfg_data (32'h0), .ext_rtcfg_ack () ); // ---------------------------------------------------- // Stream Endpoints // ---------------------------------------------------- wire [CHDR_W-1:0] m_ep0_out0_tdata; wire m_ep0_out0_tlast; wire m_ep0_out0_tvalid; wire m_ep0_out0_tready; wire [CHDR_W-1:0] s_ep0_in0_tdata; wire s_ep0_in0_tlast; wire s_ep0_in0_tvalid; wire s_ep0_in0_tready; wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; chdr_stream_endpoint #( .PROTOVER (PROTOVER), .CHDR_W (CHDR_W), .AXIS_CTRL_EN (1), .AXIS_DATA_EN (1), .NUM_DATA_I (1), .NUM_DATA_O (1), .INST_NUM (0), .CTRL_XBAR_PORT (1), .INGRESS_BUFF_SIZE (16), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep0_i ( .rfnoc_chdr_clk (rfnoc_chdr_clk ), .rfnoc_chdr_rst (rfnoc_chdr_rst ), .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), .device_id (device_id ), .s_axis_chdr_tdata (xb_to_ep0_tdata ), .s_axis_chdr_tlast (xb_to_ep0_tlast ), .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), .s_axis_chdr_tready (xb_to_ep0_tready ), .m_axis_chdr_tdata (ep0_to_xb_tdata ), .m_axis_chdr_tlast (ep0_to_xb_tlast ), .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), .m_axis_chdr_tready (ep0_to_xb_tready ), .s_axis_data_tdata ({s_ep0_in0_tdata}), .s_axis_data_tlast ({s_ep0_in0_tlast}), .s_axis_data_tvalid ({s_ep0_in0_tvalid}), .s_axis_data_tready ({s_ep0_in0_tready}), .m_axis_data_tdata ({m_ep0_out0_tdata}), .m_axis_data_tlast ({m_ep0_out0_tlast}), .m_axis_data_tvalid ({m_ep0_out0_tvalid}), .m_axis_data_tready ({m_ep0_out0_tready}), .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), .s_axis_ctrl_tready (s_ep0_ctrl_tready), .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), .m_axis_ctrl_tready (m_ep0_ctrl_tready), .strm_seq_err_stb ( ), .strm_data_err_stb ( ), .strm_route_err_stb ( ), .signal_data_err (1'b0 ) ); wire [CHDR_W-1:0] m_ep1_out0_tdata; wire m_ep1_out0_tlast; wire m_ep1_out0_tvalid; wire m_ep1_out0_tready; wire [CHDR_W-1:0] s_ep1_in0_tdata; wire s_ep1_in0_tlast; wire s_ep1_in0_tvalid; wire s_ep1_in0_tready; wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; chdr_stream_endpoint #( .PROTOVER (PROTOVER), .CHDR_W (CHDR_W), .AXIS_CTRL_EN (0), .AXIS_DATA_EN (1), .NUM_DATA_I (1), .NUM_DATA_O (1), .INST_NUM (1), .CTRL_XBAR_PORT (2), .INGRESS_BUFF_SIZE (5), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep1_i ( .rfnoc_chdr_clk (rfnoc_chdr_clk ), .rfnoc_chdr_rst (rfnoc_chdr_rst ), .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), .device_id (device_id ), .s_axis_chdr_tdata (xb_to_ep1_tdata ), .s_axis_chdr_tlast (xb_to_ep1_tlast ), .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), .s_axis_chdr_tready (xb_to_ep1_tready ), .m_axis_chdr_tdata (ep1_to_xb_tdata ), .m_axis_chdr_tlast (ep1_to_xb_tlast ), .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), .m_axis_chdr_tready (ep1_to_xb_tready ), .s_axis_data_tdata ({s_ep1_in0_tdata}), .s_axis_data_tlast ({s_ep1_in0_tlast}), .s_axis_data_tvalid ({s_ep1_in0_tvalid}), .s_axis_data_tready ({s_ep1_in0_tready}), .m_axis_data_tdata ({m_ep1_out0_tdata}), .m_axis_data_tlast ({m_ep1_out0_tlast}), .m_axis_data_tvalid ({m_ep1_out0_tvalid}), .m_axis_data_tready ({m_ep1_out0_tready}), .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), .s_axis_ctrl_tready (s_ep1_ctrl_tready), .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), .m_axis_ctrl_tready (m_ep1_ctrl_tready), .strm_seq_err_stb ( ), .strm_data_err_stb ( ), .strm_route_err_stb ( ), .signal_data_err (1'b0 ) ); wire [CHDR_W-1:0] m_ep2_out0_tdata; wire m_ep2_out0_tlast; wire m_ep2_out0_tvalid; wire m_ep2_out0_tready; wire [CHDR_W-1:0] s_ep2_in0_tdata; wire s_ep2_in0_tlast; wire s_ep2_in0_tvalid; wire s_ep2_in0_tready; wire [31:0] m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ; wire m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; chdr_stream_endpoint #( .PROTOVER (PROTOVER), .CHDR_W (CHDR_W), .AXIS_CTRL_EN (0), .AXIS_DATA_EN (1), .NUM_DATA_I (1), .NUM_DATA_O (1), .INST_NUM (2), .CTRL_XBAR_PORT (3), .INGRESS_BUFF_SIZE (16), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep2_i ( .rfnoc_chdr_clk (rfnoc_chdr_clk ), .rfnoc_chdr_rst (rfnoc_chdr_rst ), .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), .device_id (device_id ), .s_axis_chdr_tdata (xb_to_ep2_tdata ), .s_axis_chdr_tlast (xb_to_ep2_tlast ), .s_axis_chdr_tvalid (xb_to_ep2_tvalid ), .s_axis_chdr_tready (xb_to_ep2_tready ), .m_axis_chdr_tdata (ep2_to_xb_tdata ), .m_axis_chdr_tlast (ep2_to_xb_tlast ), .m_axis_chdr_tvalid (ep2_to_xb_tvalid ), .m_axis_chdr_tready (ep2_to_xb_tready ), .s_axis_data_tdata ({s_ep2_in0_tdata}), .s_axis_data_tlast ({s_ep2_in0_tlast}), .s_axis_data_tvalid ({s_ep2_in0_tvalid}), .s_axis_data_tready ({s_ep2_in0_tready}), .m_axis_data_tdata ({m_ep2_out0_tdata}), .m_axis_data_tlast ({m_ep2_out0_tlast}), .m_axis_data_tvalid ({m_ep2_out0_tvalid}), .m_axis_data_tready ({m_ep2_out0_tready}), .s_axis_ctrl_tdata (s_ep2_ctrl_tdata ), .s_axis_ctrl_tlast (s_ep2_ctrl_tlast ), .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), .s_axis_ctrl_tready (s_ep2_ctrl_tready), .m_axis_ctrl_tdata (m_ep2_ctrl_tdata ), .m_axis_ctrl_tlast (m_ep2_ctrl_tlast ), .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), .m_axis_ctrl_tready (m_ep2_ctrl_tready), .strm_seq_err_stb ( ), .strm_data_err_stb ( ), .strm_route_err_stb ( ), .signal_data_err (1'b0 ) ); wire [CHDR_W-1:0] m_ep3_out0_tdata; wire m_ep3_out0_tlast; wire m_ep3_out0_tvalid; wire m_ep3_out0_tready; wire [CHDR_W-1:0] s_ep3_in0_tdata; wire s_ep3_in0_tlast; wire s_ep3_in0_tvalid; wire s_ep3_in0_tready; wire [31:0] m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ; wire m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; chdr_stream_endpoint #( .PROTOVER (PROTOVER), .CHDR_W (CHDR_W), .AXIS_CTRL_EN (0), .AXIS_DATA_EN (1), .NUM_DATA_I (1), .NUM_DATA_O (1), .INST_NUM (3), .CTRL_XBAR_PORT (4), .INGRESS_BUFF_SIZE (5), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep3_i ( .rfnoc_chdr_clk (rfnoc_chdr_clk ), .rfnoc_chdr_rst (rfnoc_chdr_rst ), .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), .device_id (device_id ), .s_axis_chdr_tdata (xb_to_ep3_tdata ), .s_axis_chdr_tlast (xb_to_ep3_tlast ), .s_axis_chdr_tvalid (xb_to_ep3_tvalid ), .s_axis_chdr_tready (xb_to_ep3_tready ), .m_axis_chdr_tdata (ep3_to_xb_tdata ), .m_axis_chdr_tlast (ep3_to_xb_tlast ), .m_axis_chdr_tvalid (ep3_to_xb_tvalid ), .m_axis_chdr_tready (ep3_to_xb_tready ), .s_axis_data_tdata ({s_ep3_in0_tdata}), .s_axis_data_tlast ({s_ep3_in0_tlast}), .s_axis_data_tvalid ({s_ep3_in0_tvalid}), .s_axis_data_tready ({s_ep3_in0_tready}), .m_axis_data_tdata ({m_ep3_out0_tdata}), .m_axis_data_tlast ({m_ep3_out0_tlast}), .m_axis_data_tvalid ({m_ep3_out0_tvalid}), .m_axis_data_tready ({m_ep3_out0_tready}), .s_axis_ctrl_tdata (s_ep3_ctrl_tdata ), .s_axis_ctrl_tlast (s_ep3_ctrl_tlast ), .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), .s_axis_ctrl_tready (s_ep3_ctrl_tready), .m_axis_ctrl_tdata (m_ep3_ctrl_tdata ), .m_axis_ctrl_tlast (m_ep3_ctrl_tlast ), .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), .m_axis_ctrl_tready (m_ep3_ctrl_tready), .strm_seq_err_stb ( ), .strm_data_err_stb ( ), .strm_route_err_stb ( ), .signal_data_err (1'b0 ) ); // ---------------------------------------------------- // Control Crossbar // ---------------------------------------------------- wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; wire m_core_ctrl_tlast , s_core_ctrl_tlast ; wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; wire m_core_ctrl_tready, s_core_ctrl_tready; wire [31:0] m_duc0_ctrl_tdata , s_duc0_ctrl_tdata ; wire m_duc0_ctrl_tlast , s_duc0_ctrl_tlast ; wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; wire [31:0] m_ddc0_ctrl_tdata , s_ddc0_ctrl_tdata ; wire m_ddc0_ctrl_tlast , s_ddc0_ctrl_tlast ; wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; wire [31:0] m_duc1_ctrl_tdata , s_duc1_ctrl_tdata ; wire m_duc1_ctrl_tlast , s_duc1_ctrl_tlast ; wire m_duc1_ctrl_tvalid, s_duc1_ctrl_tvalid; wire m_duc1_ctrl_tready, s_duc1_ctrl_tready; wire [31:0] m_ddc1_ctrl_tdata , s_ddc1_ctrl_tdata ; wire m_ddc1_ctrl_tlast , s_ddc1_ctrl_tlast ; wire m_ddc1_ctrl_tvalid, s_ddc1_ctrl_tvalid; wire m_ddc1_ctrl_tready, s_ddc1_ctrl_tready; wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ; wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ; wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; axis_ctrl_crossbar_nxn #( .WIDTH (32), .NPORTS (8), .TOPOLOGY ("TORUS"), .INGRESS_BUFF_SIZE(5), .ROUTER_BUFF_SIZE (5), .ROUTING_ALLOC ("WORMHOLE"), .SWITCH_ALLOC ("PRIO") ) ctrl_xb_i ( .clk (rfnoc_ctrl_clk), .reset (rfnoc_ctrl_rst), .s_axis_tdata ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), .s_axis_tvalid ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), .s_axis_tlast ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), .s_axis_tready ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), .m_axis_tdata ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), .m_axis_tvalid ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), .m_axis_tlast ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), .m_axis_tready ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), .deadlock_detected() ); // ---------------------------------------------------- // RFNoC Core Kernel // ---------------------------------------------------- wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status; rfnoc_core_kernel #( .PROTOVER (PROTOVER), .DEVICE_TYPE (16'hA300), .DEVICE_FAMILY ("7SERIES"), .SAFE_START_CLKS (0), .NUM_BLOCKS (6), .NUM_STREAM_ENDPOINTS(4), .NUM_ENDPOINTS_CTRL (1), .NUM_TRANSPORTS (3), .NUM_EDGES (12), .CHDR_XBAR_PRESENT (1), .EDGE_TBL_FILE (EDGE_TBL_FILE) ) core_kernel_i ( .chdr_aclk (chdr_aclk), .chdr_aclk_locked (1'b1), .ctrl_aclk (ctrl_aclk), .ctrl_aclk_locked (1'b1), .core_arst (core_arst), .core_chdr_clk (rfnoc_chdr_clk), .core_chdr_rst (rfnoc_chdr_rst), .core_ctrl_clk (rfnoc_ctrl_clk), .core_ctrl_rst (rfnoc_ctrl_rst), .s_axis_ctrl_tdata (s_core_ctrl_tdata ), .s_axis_ctrl_tlast (s_core_ctrl_tlast ), .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), .s_axis_ctrl_tready (s_core_ctrl_tready), .m_axis_ctrl_tdata (m_core_ctrl_tdata ), .m_axis_ctrl_tlast (m_core_ctrl_tlast ), .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), .m_axis_ctrl_tready (m_core_ctrl_tready), .device_id (device_id), .rfnoc_core_config (rfnoc_core_config), .rfnoc_core_status (rfnoc_core_status) ); // ---------------------------------------------------- // Blocks // ---------------------------------------------------- // ---------------------------------------------------- // duc0 // ---------------------------------------------------- wire duc0_ce_clk; wire [CHDR_W-1:0] s_duc0_in_0_tdata ; wire s_duc0_in_0_tlast ; wire s_duc0_in_0_tvalid; wire s_duc0_in_0_tready; wire [CHDR_W-1:0] m_duc0_out_0_tdata ; wire m_duc0_out_0_tlast ; wire m_duc0_out_0_tvalid; wire m_duc0_out_0_tready; rfnoc_block_duc #( .THIS_PORTID(2), .CHDR_W(CHDR_W), .NUM_PORTS(1), .NUM_HB(3), .CIC_MAX_INTERP(255), .MTU(MTU) ) b_duc0_0 ( .rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk), .ce_clk(duc0_ce_clk), .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), .s_rfnoc_chdr_tdata ({s_duc0_in_0_tdata }), .s_rfnoc_chdr_tlast ({s_duc0_in_0_tlast }), .s_rfnoc_chdr_tvalid({s_duc0_in_0_tvalid}), .s_rfnoc_chdr_tready({s_duc0_in_0_tready}), .m_rfnoc_chdr_tdata ({m_duc0_out_0_tdata }), .m_rfnoc_chdr_tlast ({m_duc0_out_0_tlast }), .m_rfnoc_chdr_tvalid({m_duc0_out_0_tvalid}), .m_rfnoc_chdr_tready({m_duc0_out_0_tready}), .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ), .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ), .s_rfnoc_ctrl_tvalid(s_duc0_ctrl_tvalid), .s_rfnoc_ctrl_tready(s_duc0_ctrl_tready), .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ), .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ), .m_rfnoc_ctrl_tvalid(m_duc0_ctrl_tvalid), .m_rfnoc_ctrl_tready(m_duc0_ctrl_tready) ); // ---------------------------------------------------- // ddc0 // ---------------------------------------------------- wire ddc0_ce_clk; wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; wire s_ddc0_in_1_tready, s_ddc0_in_0_tready; wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; rfnoc_block_ddc #( .THIS_PORTID(3), .CHDR_W(CHDR_W), .NUM_PORTS(2), .NUM_HB(3), .CIC_MAX_DECIM(255), .MTU(MTU) ) b_ddc0_1 ( .rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk), .ce_clk(ddc0_ce_clk), .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), .s_rfnoc_chdr_tvalid({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), .s_rfnoc_chdr_tready({s_ddc0_in_1_tready, s_ddc0_in_0_tready}), .m_rfnoc_chdr_tdata ({m_ddc0_out_1_tdata , m_ddc0_out_0_tdata }), .m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }), .m_rfnoc_chdr_tvalid({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}), .m_rfnoc_chdr_tready({m_ddc0_out_1_tready, m_ddc0_out_0_tready}), .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ), .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ), .s_rfnoc_ctrl_tvalid(s_ddc0_ctrl_tvalid), .s_rfnoc_ctrl_tready(s_ddc0_ctrl_tready), .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ), .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ), .m_rfnoc_ctrl_tvalid(m_ddc0_ctrl_tvalid), .m_rfnoc_ctrl_tready(m_ddc0_ctrl_tready) ); // ---------------------------------------------------- // radio0 // ---------------------------------------------------- wire radio0_radio_clk; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; wire s_radio0_in_1_tready, s_radio0_in_0_tready; wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tready, m_radio0_out_0_tready; // ctrl_port wire [ 1-1:0] radio0_m_ctrlport_req_wr; wire [ 1-1:0] radio0_m_ctrlport_req_rd; wire [ 20-1:0] radio0_m_ctrlport_req_addr; wire [ 32-1:0] radio0_m_ctrlport_req_data; wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; wire [ 1-1:0] radio0_m_ctrlport_req_has_time; wire [ 64-1:0] radio0_m_ctrlport_req_time; wire [ 1-1:0] radio0_m_ctrlport_resp_ack; wire [ 2-1:0] radio0_m_ctrlport_resp_status; wire [ 32-1:0] radio0_m_ctrlport_resp_data; // time_keeper wire [ 64-1:0] radio0_radio_time; // x300_radio wire [ 64-1:0] radio0_radio_rx_data; wire [ 2-1:0] radio0_radio_rx_stb; wire [ 2-1:0] radio0_radio_rx_running; wire [ 64-1:0] radio0_radio_tx_data; wire [ 2-1:0] radio0_radio_tx_stb; wire [ 2-1:0] radio0_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID(4), .CHDR_W(CHDR_W), .NUM_PORTS(2), .MTU(MTU) ) b_radio0_2 ( .rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk), .radio_clk(radio0_radio_clk), .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), .m_ctrlport_req_data(radio0_m_ctrlport_req_data), .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), .m_ctrlport_req_time(radio0_m_ctrlport_req_time), .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), .radio_time(radio0_radio_time), .radio_rx_data(radio0_radio_rx_data), .radio_rx_stb(radio0_radio_rx_stb), .radio_rx_running(radio0_radio_rx_running), .radio_tx_data(radio0_radio_tx_data), .radio_tx_stb(radio0_radio_tx_stb), .radio_tx_running(radio0_radio_tx_running), .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) ); // ---------------------------------------------------- // duc1 // ---------------------------------------------------- wire duc1_ce_clk; wire [CHDR_W-1:0] s_duc1_in_0_tdata ; wire s_duc1_in_0_tlast ; wire s_duc1_in_0_tvalid; wire s_duc1_in_0_tready; wire [CHDR_W-1:0] m_duc1_out_0_tdata ; wire m_duc1_out_0_tlast ; wire m_duc1_out_0_tvalid; wire m_duc1_out_0_tready; rfnoc_block_duc #( .THIS_PORTID(5), .CHDR_W(CHDR_W), .NUM_PORTS(1), .NUM_HB(3), .CIC_MAX_INTERP(255), .MTU(MTU) ) b_duc1_3 ( .rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk), .ce_clk(duc1_ce_clk), .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), .s_rfnoc_chdr_tdata ({s_duc1_in_0_tdata }), .s_rfnoc_chdr_tlast ({s_duc1_in_0_tlast }), .s_rfnoc_chdr_tvalid({s_duc1_in_0_tvalid}), .s_rfnoc_chdr_tready({s_duc1_in_0_tready}), .m_rfnoc_chdr_tdata ({m_duc1_out_0_tdata }), .m_rfnoc_chdr_tlast ({m_duc1_out_0_tlast }), .m_rfnoc_chdr_tvalid({m_duc1_out_0_tvalid}), .m_rfnoc_chdr_tready({m_duc1_out_0_tready}), .s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata ), .s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast ), .s_rfnoc_ctrl_tvalid(s_duc1_ctrl_tvalid), .s_rfnoc_ctrl_tready(s_duc1_ctrl_tready), .m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata ), .m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast ), .m_rfnoc_ctrl_tvalid(m_duc1_ctrl_tvalid), .m_rfnoc_ctrl_tready(m_duc1_ctrl_tready) ); // ---------------------------------------------------- // ddc1 // ---------------------------------------------------- wire ddc1_ce_clk; wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ; wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ; wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid; wire s_ddc1_in_1_tready, s_ddc1_in_0_tready; wire [CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ; wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ; wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid; wire m_ddc1_out_1_tready, m_ddc1_out_0_tready; rfnoc_block_ddc #( .THIS_PORTID(6), .CHDR_W(CHDR_W), .NUM_PORTS(2), .NUM_HB(3), .CIC_MAX_DECIM(255), .MTU(MTU) ) b_ddc1_4 ( .rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk), .ce_clk(ddc1_ce_clk), .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), .s_rfnoc_chdr_tdata ({s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }), .s_rfnoc_chdr_tlast ({s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }), .s_rfnoc_chdr_tvalid({s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}), .s_rfnoc_chdr_tready({s_ddc1_in_1_tready, s_ddc1_in_0_tready}), .m_rfnoc_chdr_tdata ({m_ddc1_out_1_tdata , m_ddc1_out_0_tdata }), .m_rfnoc_chdr_tlast ({m_ddc1_out_1_tlast , m_ddc1_out_0_tlast }), .m_rfnoc_chdr_tvalid({m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid}), .m_rfnoc_chdr_tready({m_ddc1_out_1_tready, m_ddc1_out_0_tready}), .s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata ), .s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast ), .s_rfnoc_ctrl_tvalid(s_ddc1_ctrl_tvalid), .s_rfnoc_ctrl_tready(s_ddc1_ctrl_tready), .m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata ), .m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast ), .m_rfnoc_ctrl_tvalid(m_ddc1_ctrl_tvalid), .m_rfnoc_ctrl_tready(m_ddc1_ctrl_tready) ); // ---------------------------------------------------- // radio1 // ---------------------------------------------------- wire radio1_radio_clk; wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; wire s_radio1_in_1_tready, s_radio1_in_0_tready; wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; wire m_radio1_out_1_tready, m_radio1_out_0_tready; // ctrl_port wire [ 1-1:0] radio1_m_ctrlport_req_wr; wire [ 1-1:0] radio1_m_ctrlport_req_rd; wire [ 20-1:0] radio1_m_ctrlport_req_addr; wire [ 32-1:0] radio1_m_ctrlport_req_data; wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; wire [ 1-1:0] radio1_m_ctrlport_req_has_time; wire [ 64-1:0] radio1_m_ctrlport_req_time; wire [ 1-1:0] radio1_m_ctrlport_resp_ack; wire [ 2-1:0] radio1_m_ctrlport_resp_status; wire [ 32-1:0] radio1_m_ctrlport_resp_data; // time_keeper wire [ 64-1:0] radio1_radio_time; // x300_radio wire [ 64-1:0] radio1_radio_rx_data; wire [ 2-1:0] radio1_radio_rx_stb; wire [ 2-1:0] radio1_radio_rx_running; wire [ 64-1:0] radio1_radio_tx_data; wire [ 2-1:0] radio1_radio_tx_stb; wire [ 2-1:0] radio1_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID(7), .CHDR_W(CHDR_W), .NUM_PORTS(2), .MTU(MTU) ) b_radio1_5 ( .rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk), .radio_clk(radio1_radio_clk), .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), .m_ctrlport_req_wr(radio1_m_ctrlport_req_wr), .m_ctrlport_req_rd(radio1_m_ctrlport_req_rd), .m_ctrlport_req_addr(radio1_m_ctrlport_req_addr), .m_ctrlport_req_data(radio1_m_ctrlport_req_data), .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), .m_ctrlport_req_time(radio1_m_ctrlport_req_time), .m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack), .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), .radio_time(radio1_radio_time), .radio_rx_data(radio1_radio_rx_data), .radio_rx_stb(radio1_radio_rx_stb), .radio_rx_running(radio1_radio_rx_running), .radio_tx_data(radio1_radio_tx_data), .radio_tx_stb(radio1_radio_tx_stb), .radio_tx_running(radio1_radio_tx_running), .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), .s_rfnoc_chdr_tvalid({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), .s_rfnoc_chdr_tready({s_radio1_in_1_tready, s_radio1_in_0_tready}), .m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }), .m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }), .m_rfnoc_chdr_tvalid({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), .m_rfnoc_chdr_tready({m_radio1_out_1_tready, m_radio1_out_0_tready}), .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ), .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ), .s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid), .s_rfnoc_ctrl_tready(s_radio1_ctrl_tready), .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ), .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ), .m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid), .m_rfnoc_ctrl_tready(m_radio1_ctrl_tready) ); // ---------------------------------------------------- // Static Router // ---------------------------------------------------- assign s_duc0_in_0_tdata = m_ep0_out0_tdata ; assign s_duc0_in_0_tlast = m_ep0_out0_tlast ; assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; assign m_ep0_out0_tready = s_duc0_in_0_tready; assign s_radio0_in_0_tdata = m_duc0_out_0_tdata ; assign s_radio0_in_0_tlast = m_duc0_out_0_tlast ; assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid; assign m_duc0_out_0_tready = s_radio0_in_0_tready; assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata ; assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast ; assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid; assign m_radio0_out_0_tready = s_ddc0_in_0_tready; assign s_ep0_in0_tdata = m_ddc0_out_0_tdata ; assign s_ep0_in0_tlast = m_ddc0_out_0_tlast ; assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid; assign m_ddc0_out_0_tready = s_ep0_in0_tready; assign s_ddc0_in_1_tdata = m_radio0_out_1_tdata ; assign s_ddc0_in_1_tlast = m_radio0_out_1_tlast ; assign s_ddc0_in_1_tvalid = m_radio0_out_1_tvalid; assign m_radio0_out_1_tready = s_ddc0_in_1_tready; assign s_ep1_in0_tdata = m_ddc0_out_1_tdata ; assign s_ep1_in0_tlast = m_ddc0_out_1_tlast ; assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid; assign m_ddc0_out_1_tready = s_ep1_in0_tready; assign s_duc1_in_0_tdata = m_ep2_out0_tdata ; assign s_duc1_in_0_tlast = m_ep2_out0_tlast ; assign s_duc1_in_0_tvalid = m_ep2_out0_tvalid; assign m_ep2_out0_tready = s_duc1_in_0_tready; assign s_radio1_in_0_tdata = m_duc1_out_0_tdata ; assign s_radio1_in_0_tlast = m_duc1_out_0_tlast ; assign s_radio1_in_0_tvalid = m_duc1_out_0_tvalid; assign m_duc1_out_0_tready = s_radio1_in_0_tready; assign s_ddc1_in_0_tdata = m_radio1_out_0_tdata ; assign s_ddc1_in_0_tlast = m_radio1_out_0_tlast ; assign s_ddc1_in_0_tvalid = m_radio1_out_0_tvalid; assign m_radio1_out_0_tready = s_ddc1_in_0_tready; assign s_ep2_in0_tdata = m_ddc1_out_0_tdata ; assign s_ep2_in0_tlast = m_ddc1_out_0_tlast ; assign s_ep2_in0_tvalid = m_ddc1_out_0_tvalid; assign m_ddc1_out_0_tready = s_ep2_in0_tready; assign s_ddc1_in_1_tdata = m_radio1_out_1_tdata ; assign s_ddc1_in_1_tlast = m_radio1_out_1_tlast ; assign s_ddc1_in_1_tvalid = m_radio1_out_1_tvalid; assign m_radio1_out_1_tready = s_ddc1_in_1_tready; assign s_ep3_in0_tdata = m_ddc1_out_1_tdata ; assign s_ep3_in0_tlast = m_ddc1_out_1_tlast ; assign s_ep3_in0_tvalid = m_ddc1_out_1_tvalid; assign m_ddc1_out_1_tready = s_ep3_in0_tready; // ---------------------------------------------------- // Unused Ports // ---------------------------------------------------- assign s_radio0_in_1_tdata = {CHDR_W{1'b0}}; assign s_radio0_in_1_tlast = 1'b0; assign s_radio0_in_1_tvalid = 1'b0; assign s_radio1_in_1_tdata = {CHDR_W{1'b0}}; assign s_radio1_in_1_tlast = 1'b0; assign s_radio1_in_1_tvalid = 1'b0; assign m_ep1_out0_tready = 1'b1; assign m_ep3_out0_tready = 1'b1; // ---------------------------------------------------- // Clock Domains // ---------------------------------------------------- assign radio0_radio_clk = radio_clk; assign ddc0_ce_clk = ce_clk; assign duc0_ce_clk = ce_clk; assign radio1_radio_clk = radio_clk; assign ddc1_ce_clk = ce_clk; assign duc1_ce_clk = ce_clk; // ---------------------------------------------------- // IO Port Connection // ---------------------------------------------------- // Master/Slave Connections: assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr; assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd; assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr; assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data; assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en; assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time; assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time; assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack; assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; assign radio0_radio_rx_data = radio_rx_data_radio0; assign radio0_radio_rx_stb = radio_rx_stb_radio0; assign radio_rx_running_radio0 = radio0_radio_rx_running; assign radio_tx_data_radio0 = radio0_radio_tx_data; assign radio0_radio_tx_stb = radio_tx_stb_radio0; assign radio_tx_running_radio0 = radio0_radio_tx_running; assign radio1_radio_rx_data = radio_rx_data_radio1; assign radio1_radio_rx_stb = radio_rx_stb_radio1; assign radio_rx_running_radio1 = radio1_radio_rx_running; assign radio_tx_data_radio1 = radio1_radio_tx_data; assign radio1_radio_tx_stb = radio_tx_stb_radio1; assign radio_tx_running_radio1 = radio1_radio_tx_running; // Broadcaster/Listener Connections: assign radio0_radio_time = radio_time; assign radio1_radio_time = radio_time; endmodule