xilinx.com xci unknown 1.0 pcie_clk_gen false 100000000 false 100000000 false 100000000 false 100000000 100000000 0 0 0.0 100000000 0 0 0.0 100000000 0 0 0.0 1 LEVEL_HIGH 100000000 0 0 0.0 0 0 100000000 0 0 0.0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.0 AXI4LITE READ_WRITE 0 0 0 0 0 0 MMCM cddcdone cddcreq 0000 0000 CLKFB_IN_N CLKFB_IN CLKFB_IN_P SINGLE CLKFB_OUT_N CLKFB_OUT CLKFB_OUT_P CLKFB_STOPPED 800.0 100.0 0000 0000 40.00000 0000 0000 200.00000 BUFH 50.0 false 40.00000 0.000 50.000 40 0.000 1 0000 0000 100.000 BUFH 50.0 false 200.00000 0.000 50.000 200 0.000 1 1 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 VCO CLK_IN_SEL CLK_OUT1 CLK_OUT2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 CLK_VALID NA DADDR DCLK DEN DIN 0000 1 0.2 0.04 0.04 0.04 0.04 0.04 DOUT DRDY DWE 49.000 1.000 0 0 0 0 0 0 0 0 FDBK_AUTO 0000 0000 0 Input Clock Freq (MHz) Input Jitter (UI) __primary_________125.000____________0.100 no_secondary_input_clock INPUT_CLK_STOPPED 0 Units_MHz No_Jitter LOCKED 0000 0000 0000 false false false false false false false false OPTIMIZED 8.000 0.000 FALSE 8.000 10.0 25.000 0.500 0.000 FALSE 5 0.500 0.000 FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE ZHOLD 1 None 0.100 0.010 FALSE 64.000 2.000 2 0 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) CLK_OUT1__40.00000______0.000______50.0______353.417_____96.948 CLK_OUT2__200.00000______0.000______50.0______192.299_____96.948 no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output 0 0 128.000 1.000 WAVEFORM UNKNOWN false false false false false OPTIMIZED 1 0.000 1.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 No notes 0.010 POWER_DOWN 0000 1 CLK_IN1 PLL AUTO 125.000 0.100 10.000 No_buffer PSCLK PSDONE PSEN PSINCDEC 100.0 0 RESET 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 4000 0.004 STATUS 11 32 100.0 100.0 100.0 100.0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 1866.000 800.000 pcie_clk_gen MMCM false DONE cddcdone cddcreq CLKFB_IN_N CLKFB_IN CLKFB_IN_P SINGLE CLKFB_OUT_N CLKFB_OUT CLKFB_OUT_P CLKFB_STOPPED 800.0 0.100 100.0 0.010 BUFH 1181.857 false 265.359 50.000 40 0.000 1 true BUFH 440.890 false 265.359 50.000 200 0.000 1 true BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false 600.000 Custom Custom CLK_IN_SEL CLK_OUT1 false CLK_OUT2 false clk_out3 false clk_out4 false clk_out5 false clk_out6 false clk_out7 false CLK_VALID MANUAL pcie_clk_gen DADDR DCLK DEN Custom Custom DIN DOUT DRDY DWE false false false false false false false false false FDBK_AUTO INPUT_CLK_STOPPED frequency Enable_AXI Units_MHz Units_UI UI No_Jitter LOCKED OPTIMIZED 8 0.000 false 8.000 10.0 25 0.500 0.000 false 5 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false ZHOLD 1 None 0.100 0.010 false 2 false false false WAVEFORM false UNKNOWN OPTIMIZED 4 0.000 10.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 None 0.010 POWER_DOWN 1 CLK_IN1 PLL MMCM_ADV 125.000 0.100 10.000 No_buffer PSCLK PSDONE PSEN PSINCDEC 100.0 REL_PRIMARY Custom RESET ACTIVE_HIGH 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 250 0.004 STATUS empty 100.0 100.0 100.0 100.0 false false false false false false false true false false true false false false true false true false false false kintex7 xc7k410t ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 8 TRUE . . 2021.1 OUT_OF_CONTEXT