xilinx.com xci unknown 1.0 fifo_4k_2clk 100000000 0 0 0.0 100000000 0 0 0.0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.0 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0.0 100000000 0 0 0.0 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.0 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0.0 0 0 0 0 0 0 0 1 1 1 1 1 4 0 32 1 1 1 64 1 8 1 1 1 1 0 0 9 BlankString 72 1 32 64 1 64 2 0 72 0 1 0 0 0 0 0 0 0 0 zynq 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 2 1 1 1 1 1 1 0 0 1 BlankString 0 0 0 0 0 1 512x72 1kx18 512x36 1kx36 512x36 1kx36 512x36 4 1022 1022 1022 1022 1022 1022 5 0 0 0 0 0 0 0 511 1023 1023 1023 1023 1023 1023 510 0 0 0 0 0 0 0 0 0 10 512 1 9 0 0 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 10 512 1024 16 1024 16 1024 16 1 9 10 4 10 4 10 4 1 32 0 0 false false false 0 0 Slave_Interface_Clock_Enable Common_Clock fifo_4k_2clk 64 false 9 true false 0 4 1022 1022 1022 1022 1022 1022 5 false false false false false false false false false Hard_ECC false false false false false false true false false true Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Independent_Clocks_Block_RAM 1 511 1023 1023 1023 1023 1023 1023 510 false false false 0 Native false false false false false false false false false false false false false false 72 512 1024 16 1024 16 1024 16 false 72 512 Embedded_Reg false false Active_High Active_High AXI4 First_Word_Fall_Through No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold READ_WRITE 0 1 true 10 Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered true Asynchronous_Reset false 0 0 0 0 0 4 false false Active_High Active_High true false false true false Active_High 0 false Active_High 1 true 10 false FIFO false false false false FIFO FIFO 2 2 false FIFO FIFO FIFO zynq xc7z100 ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 5 TRUE . . 2021.1 OUT_OF_CONTEXT