//------------------------------------------------------------------------------ // File : gige_sfp_mdio_block.v // Author : Xilinx Inc. //------------------------------------------------------------------------------ // (c) Copyright 2009 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // //------------------------------------------------------------------------------ // Description: This Core Block Level wrapper connects the core to a // Series-7 Transceiver. // // // ------------------------------------------------------------ // | Core Block wrapper | // | | // | ------------------ ----------------- | // | | Core | | Transceiver | | // | | | | | | // | | | | | | // | | | | | | // ---------->| GMII |--------->| TXP |--------> // | | Tx | | TXN | | // | | | | | | // | | | | | | // | | | | | | // | | | | | | // | | | | | | // | | GMII | | RXP | | // <----------| Rx |<---------| RXN |<-------- // | | | | | | // | ------------------ ----------------- | // | | // ------------------------------------------------------------ // // `timescale 1 ps/1 ps //------------------------------------------------------------------------------ // The module declaration for the Core Block wrapper. //------------------------------------------------------------------------------ module gige_sfp_mdio_block ( // Transceiver Interface //---------------------- input gtrefclk, // Very high quality 125MHz clock for GT transceiver. output txp, // Differential +ve of serial transmission from PMA to PMD. output txn, // Differential -ve of serial transmission from PMA to PMD. input rxp, // Differential +ve for serial reception from PMD to PMA. input rxn, // Differential -ve for serial reception from PMD to PMA. output txoutclk, // txoutclk from GT transceiver (62.5MHz) output resetdone, // The GT transceiver has completed its reset cycle input mmcm_locked, // locked indication from MMCM input userclk, // 62.5MHz global clock. input userclk2, // 125MHz global clock. input independent_clock_bufg,// 200MHz Independent clock, input pma_reset, // transceiver PMA reset signal // GMII Interface //--------------- input [7:0] gmii_txd, // Transmit data from client MAC. input gmii_tx_en, // Transmit control signal from client MAC. input gmii_tx_er, // Transmit control signal from client MAC. output [7:0] gmii_rxd, // Received Data to client MAC. output gmii_rx_dv, // Received control signal to client MAC. output gmii_rx_er, // Received control signal to client MAC. output gmii_isolate, // Tristate control to electrically isolate GMII. // Management: MDIO Interface //--------------------------- input mdc, // Management Data Clock input mdio_i, // Management Data In output mdio_o, // Management Data Out output mdio_t, // Management Data Tristate input [4:0] phyad, // Port address for MDIO. input [4:0] configuration_vector, // Alternative to MDIO interface. input configuration_valid, // Validation signal for Config vector // General IO's //------------- output [15:0] status_vector, // Core status. input reset, // Asynchronous reset for entire core. input signal_detect // Input from PMD to indicate presence of optical input. ); //--------------------------------------------------------------------------- // Internal signals used in this block level wrapper. //--------------------------------------------------------------------------- // Core <=> Transceiver interconnect wire plllock; // The PLL Locked status of the Transceiver wire mgt_rx_reset; // Reset for the receiver half of the Transceiver wire mgt_tx_reset; // Reset for the transmitter half of the Transceiver wire [1:0] rxbufstatus; // Elastic Buffer Status (bit 1 asserted indicates overflow or underflow). wire rxchariscomma; // Comma detected in RXDATA. wire rxcharisk; // K character received (or extra data bit) in RXDATA. wire [2:0] rxclkcorcnt; // Indicates clock correction. wire [7:0] rxdata; // Data after 8B/10B decoding. wire rxrundisp; // Running Disparity after current byte, becomes 9th data bit when RXNOTINTABLE='1'. wire rxdisperr; // Disparity-error in RXDATA. wire rxnotintable; // Non-existent 8B/10 code indicated. wire txbuferr; // TX Buffer error (overflow or underflow). wire loopback; // Set the Transceiver for loopback. wire powerdown; // Powerdown the Transceiver wire txchardispmode; // Set running disparity for current byte. wire txchardispval; // Set running disparity value. wire txcharisk; // K character transmitted in TXDATA. wire [7:0] txdata; // Data for 8B/10B encoding. wire enablealign; // Allow the transceivers to serially realign to a comma character. //--------------------------------------------------------------------------- // Instantiate the core //--------------------------------------------------------------------------- gige_sfp_mdio gig_eth_pcs_pma_core ( .mgt_rx_reset (mgt_rx_reset), .mgt_tx_reset (mgt_tx_reset), .userclk (userclk2), .userclk2 (userclk2), .dcm_locked (mmcm_locked), .rxbufstatus (rxbufstatus), .rxchariscomma (rxchariscomma), .rxcharisk (rxcharisk), .rxclkcorcnt (rxclkcorcnt), .rxdata (rxdata), .rxdisperr (rxdisperr), .rxnotintable (rxnotintable), .rxrundisp (rxrundisp), .txbuferr (txbuferr), .powerdown (powerdown), .txchardispmode (txchardispmode), .txchardispval (txchardispval), .txcharisk (txcharisk), .txdata (txdata), .enablealign (enablealign), .gmii_txd (gmii_txd), .gmii_tx_en (gmii_tx_en), .gmii_tx_er (gmii_tx_er), .gmii_rxd (gmii_rxd), .gmii_rx_dv (gmii_rx_dv), .gmii_rx_er (gmii_rx_er), .gmii_isolate (gmii_isolate), .mdc (mdc), .mdio_in (mdio_i), .mdio_out (mdio_o), .mdio_tri (mdio_t), .phyad (phyad), .configuration_vector (configuration_vector), .configuration_valid (configuration_valid), .status_vector (status_vector), .reset (reset), .signal_detect (signal_detect) ); //--------------------------------------------------------------------------- // Component Instantiation for the Series-7 Transceiver wrapper //--------------------------------------------------------------------------- gige_sfp_mdio_transceiver transceiver_inst ( .encommaalign (enablealign), .loopback (loopback), .powerdown (powerdown), .usrclk (userclk), .usrclk2 (userclk2), .independent_clock (independent_clock_bufg), .data_valid (status_vector[1]), .txreset (mgt_tx_reset), .txchardispmode (txchardispmode), .txchardispval (txchardispval), .txcharisk (txcharisk), .txdata (txdata), .rxreset (mgt_rx_reset), .rxchariscomma (rxchariscomma), .rxcharisk (rxcharisk), .rxclkcorcnt (rxclkcorcnt), .rxdata (rxdata), .rxdisperr (rxdisperr), .rxnotintable (rxnotintable), .rxrundisp (rxrundisp), .rxbuferr (rxbufstatus[1]), .txbuferr (txbuferr), .plllkdet (plllock), .txoutclk (txoutclk), .txn (txn), .txp (txp), .rxn (rxn), .rxp (rxp), .gtrefclk (gtrefclk), .pmareset (pma_reset), .mmcm_locked (mmcm_locked), .resetdone (resetdone) ); // Unused assign rxbufstatus[0] = 1'b0; // Loopback is performed in the core itself. To alternatively use // Transceiver loopback, please drive this port appropriately. assign loopback = 1'b0; endmodule // gige_sfp_mdio_block