The following files were generated for 'hbdec2' in directory
/home/mwest/git/fpgadev/usrp3/top/b205/coregen_dsp/

Opens the IP Customization GUI:
   Allows the user to customize or recustomize the IP instance.

   * hbdec2.mif
   * hbdec2_reload_order.txt

ISE file generator:
   Add description here...

   * hbdec2_flist.txt

Model Parameter Resolution:
   Resolves generated model parameter values on the component instance.

   * hbdec2.mif
   * hbdec2_reload_order.txt

XCO file generator:
   Generate an XCO file for compatibility with legacy flows.

   * hbdec2.xco

Creates an implementation netlist:
   Creates an implementation netlist for the IP.

   * hbdec2.ngc
   * hbdec2.v
   * hbdec2.veo
   * hbdec2COEFF_auto0_0.mif
   * hbdec2COEFF_auto0_1.mif
   * hbdec2COEFF_auto0_2.mif
   * hbdec2COEFF_auto_HALFBAND_CENTRE0.mif
   * hbdec2_reload_addrfilt_decode_rom.mif
   * hbdec2filt_decode_rom.mif

Creates an HDL instantiation template:
   Creates an HDL instantiation template for the IP.

   * hbdec2.veo

IP Symbol Generator:
   Generate an IP symbol based on the current project options'.

   * hbdec2.asy

Generate ISE metadata:
   Create a metadata file for use when including this core in ISE designs

   * hbdec2_xmdf.tcl

Generate ISE subproject:
   Create an ISE subproject for use when including this core in ISE designs

   * hbdec2.gise
   * hbdec2.xise

Deliver Readme:
   Readme file for the IP.

   * hbdec2_readme.txt

Generate FLIST file:
   Text file listing all of the output files produced when a customized core was
   generated in the CORE Generator.

   * hbdec2_flist.txt

Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.