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fpga: sim: Workaround Vivado bug in ChdrIfaceBfm_tb

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Original-commit: 9e4de0d0b7a1a35a5b3220a605c329e60f8b5e83
This commit is contained in:
Humberto Jimenez
2022-08-25 13:55:30 -05:00
committed by skooNI
parent 3fc345d3ae
commit fb83fe3830
2 changed files with 77 additions and 57 deletions
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sim/rfnoc/test/ChdrIfaceBfm/ChdrIfaceBfm_all_tb.sv
+11 -2
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@@ -1,5 +1,5 @@
//
// Copyright 2020 Ettus Research, A National Instruments Company
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -44,10 +44,19 @@ module ChdrIfaceBfm_all_tb();
genvar i;
for (i = 0; i < NUM_TESTS; i++) begin : gen_test_config
// There is an internal bug in Vivado 2021.1 that prevents all the tests to
// run at the same time. Therefore, we are splitting the ADV tests and
// running them separately.
ChdrIfaceBfm_tb #(
.CHDR_W (tests[i].CHDR_W),
.ITEM_W (tests[i].ITEM_W)
.ITEM_W (tests[i].ITEM_W),
.ADV (0)
) ChdrIfaceBfm_tb_i ();
ChdrIfaceBfm_tb #(
.CHDR_W (tests[i].CHDR_W),
.ITEM_W (tests[i].ITEM_W),
.ADV (1)
) ChdrIfaceBfm_tb_adv_i ();
end : gen_test_config
endmodule : ChdrIfaceBfm_all_tb
sim/rfnoc/test/ChdrIfaceBfm/ChdrIfaceBfm_tb.sv
+25 -14
View File
@@ -1,5 +1,5 @@
//
// Copyright 2020 Ettus Research, A National Instruments Company
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -11,7 +11,8 @@
module ChdrIfaceBfm_tb #(
parameter int CHDR_W = 64,
parameter int ITEM_W = 32,
parameter int SPP = 64
parameter int SPP = 64,
parameter bit ADV = 0
);
`include "test_exec.svh"
@@ -518,6 +519,27 @@ module ChdrIfaceBfm_tb #(
// Test Sequences
//-------------------------------------------------------------------------
// There is an internal bug in Vivado 2021.1 that prevents all of these
// tests to run at the same time. Therefore, we are splitting the *_adv
// tests and running them separately in the *all_tb file.
if (ADV) begin
test.start_test("Test send_packets_items() / recv_packets_items_adv(num_items)", 10ms);
for (int i = 0; i < 1000; i++) test_recv_packets_items_adv(TEST_NUM_ITEMS);
test.end_test();
test.start_test("Test send_packets_items() / recv_packets_items_adv(num_items)", 10ms);
for (int i = 0; i < 1000; i++) test_recv_packets_items_adv(TEST_NUM_ITEMS);
test.end_test();
test.start_test("Test send_packets_items() / recv_packets_items_adv(eob)", 10ms);
for (int i = 0; i < 1000; i++) test_recv_packets_items_adv(TEST_EOB);
test.end_test();
test.start_test("Test send_packets_items() / recv_packets_items_adv(eov)", 10ms);
for (int i = 0; i < 1000; i++) test_recv_packets_items_adv(TEST_EOV);
test.end_test();
end else begin
test.start_test("Test send() / recv()", 10ms);
for (int i = 0; i < 1000; i++) test_send(TEST_RECV);
test.end_test();
@@ -549,18 +571,7 @@ module ChdrIfaceBfm_tb #(
test.start_test("Test send_packets_items() / recv_packets_items(eov)", 10ms);
for (int i = 0; i < 1000; i++) test_recv_packets_items(TEST_EOV);
test.end_test();
test.start_test("Test send_packets_items() / recv_packets_items_adv(num_items)", 10ms);
for (int i = 0; i < 1000; i++) test_recv_packets_items_adv(TEST_NUM_ITEMS);
test.end_test();
test.start_test("Test send_packets_items() / recv_packets_items_adv(eob)", 10ms);
for (int i = 0; i < 1000; i++) test_recv_packets_items_adv(TEST_EOB);
test.end_test();
test.start_test("Test send_packets_items() / recv_packets_items_adv(eov)", 10ms);
for (int i = 0; i < 1000; i++) test_recv_packets_items_adv(TEST_EOV);
test.end_test();
end
// Make sure we don't get any more packets. Wait for more than a packet of
// worth of time the check if we've received anything.