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fpga: x400: Add support for X4C, C1, and UC variants

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Moves X4C_100, X4C_200, C1_100, and C1_200 from experimental to
available targets and makes the needed changes to allow them to build
successfully.

Adds support for "UC" FPGA variant. U indicates that QSFP0 is unused
and C indicates that QSFP1 is 100 GbE.

Adds experimental CG_200 variant.


Original-commit: cb9609c886b156e22ae9d879fffad8d060f2ca2d
This commit is contained in:
Wade Fife
2023-02-24 08:07:17 -06:00
parent 0e65ae3c86
commit fae19151c4
4 changed files with 370 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/Makefile
+64 -38
View File
@@ -41,7 +41,6 @@ QSFP1_10GBE = QSFP1_0=$(MGT_10GbE)
QSFP1_4X10GBE = QSFP1_0=$(MGT_10GbE) QSFP1_1=$(MGT_10GbE) QSFP1_2=$(MGT_10GbE) QSFP1_3=$(MGT_10GbE)
QSFP1_100GBE = QSFP1_0=$(MGT_100GbE) QSFP1_1=$(MGT_Disabled) QSFP1_2=$(MGT_Disabled) QSFP1_3=$(MGT_Disabled)
# Target specific variables
X410_IP: DEFS += $(QSFP0_10GBE) RFBW_100M=1
X410_X1_100: DEFS += $(QSFP0_10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
@@ -49,7 +48,10 @@ X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_100M=1 DRAM_CH=4*$(D
X410_X4_100: DEFS += $(QSFP0_4X10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_100M=1 DRAM_CH=0
X410_C1_100: DEFS += $(QSFP0_100GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_UC_100: DEFS += $(QSFP1_100GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_C1_200: DEFS += $(QSFP0_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_UC_200: DEFS += $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_CG_200: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X1_200: DEFS += $(QSFP0_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4_200: DEFS += $(QSFP0_4X10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
@@ -58,6 +60,7 @@ X410_X1_400: DEFS += $(QSFP0_10GBE) RFBW_400M=1 DRAM_CH=4*$(D
X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_X4_400: DEFS += $(QSFP0_4X10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_C1_400: DEFS += $(QSFP0_100GBE) RFBW_400M=1 DRAM_CH=0
X410_UC_400: DEFS += $(QSFP1_100GBE) RFBW_400M=1 DRAM_CH=0
X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_400M=1 DRAM_CH=0
# DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to
@@ -72,6 +75,8 @@ DEFS += BUILD_SEED=$(BUILD_SEED)
# Defaults specific to the various targets:
X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_x4c_200_static_router.hex)
X410_CG_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_cg_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_cg_200_static_router.hex)
X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
X410_400_128_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_128_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_128_static_router.hex)
@@ -107,21 +112,29 @@ endif
##
##Available Targets
##------------|-----------|-----------------|-----------------|------------
##Target | Bandwidth | QSFP0 | QSFP1 | DRAM
##------------|-----------|-----------------|-----------------|------------
##X410_X1_100 | 100 MHz | 10 GbE (Lane 0) | None | 64b x 4 Ch
##X410_XG_100 | 100 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
##X410_X4_100 | 100 MHz | 4 x 10 GbE | None | 64b x 4 Ch
##X410_X1_200 | 200 MHz | 10 GbE (Lane 0) | None | 64b x 4 Ch
##X410_XG_200 | 200 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
##X410_X4_200 | 200 MHz | 4 x 10 GbE | None | 64b x 4 Ch
##X410_X1_400 | 400 MHz | 10 GbE (Lane 0) | None | 128b x 4 Ch
##X410_XG_400 | 400 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch
##X410_X4_400 | 400 MHz | 4 x 10 GbE | None | 128b x 4 Ch
##X410_C1_400 | 400 MHz | 100 GbE | None | None
##X410_CG_400 | 400 MHz | 100 GbE | 100 GbE | None
##* Note: Not all targets are shipped with UHD
##-------------|-----------|-----------------|-----------------|------------
##Target | Bandwidth | QSFP0 | QSFP1 | DRAM
##-------------|-----------|-----------------|-----------------|------------
##X410_X1_100 | 100 MHz | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
##X410_XG_100 | 100 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
##X410_X4_100 | 100 MHz | 4 x 10 GbE | Unused | 64b x 4 Ch
##X410_X4C_100 | 100 MHz | 4 x 10 GbE | 100 GbE | Unused
##X410_C1_100 | 100 MHz | 100 GbE | Unused | 64b x 4 Ch
##X410_UC_100 | 100 MHz | Unused | 100 GbE | 64b x 4 Ch
##X410_X1_200 | 200 MHz | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
##X410_XG_200 | 200 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
##X410_X4_200 | 200 MHz | 4 x 10 GbE | Unused | 64b x 4 Ch
##X410_X4C_200 | 200 MHz | 4 x 10 GbE | 100 GbE | Unused
##X410_C1_200 | 200 MHz | 100 GbE | Unused | 64b x 4 Ch
##X410_UC_200 | 200 MHz | Unused | 100 GbE | 64b x 4 Ch
##X410_X1_400 | 400 MHz | 10 GbE (Lane 0) | Unused | 128b x 4 Ch
##X410_XG_400 | 400 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch
##X410_X4_400 | 400 MHz | 4 x 10 GbE | Unused | 128b x 4 Ch
##X410_C1_400 | 400 MHz | 100 GbE | Unused | Unused
##X410_UC_400 | 400 MHz | Unused | 100 GbE | Unused
##X410_CG_400 | 400 MHz | 100 GbE | 100 GbE | Unused
##* Note: Not all targets are shipped with UHD.
##* Note: Some YAML configurations might not use all available DRAM channels.
X410_X1_100: X410_IP build/usrp_x410_fpga_X1_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
@@ -135,6 +148,18 @@ X410_X4_100: X410_IP build/usrp_x410_fpga_X4_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X4_100)
X410_X4C_100: X410_IP build/usrp_x410_fpga_X4C_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_X4C_200_DEFAULTS))
$(call post_build,X410,X4C_100)
X410_C1_100: X410_IP build/usrp_x410_fpga_C1_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
$(call post_build,X410,C1_100)
X410_UC_100: X410_IP build/usrp_x410_fpga_UC_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
$(call post_build,X410,UC_100)
X410_X1_200: X410_IP build/usrp_x410_fpga_X1_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X1_200)
@@ -147,6 +172,18 @@ X410_X4_200: X410_IP build/usrp_x410_fpga_X4_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X4_200)
X410_X4C_200: X410_IP build/usrp_x410_fpga_X4C_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_X4C_200_DEFAULTS))
$(call post_build,X410,X4C_200)
X410_C1_200: X410_IP build/usrp_x410_fpga_C1_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
$(call post_build,X410,C1_200)
X410_UC_200: X410_IP build/usrp_x410_fpga_UC_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
$(call post_build,X410,UC_200)
X410_X1_400: X410_IP build/usrp_x410_fpga_X1_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
$(call post_build,X410,X1_400)
@@ -163,43 +200,32 @@ X410_C1_400: X410_IP build/usrp_x410_fpga_C1_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,C1_400)
X410_UC_400: X410_IP build/usrp_x410_fpga_UC_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,UC_400)
X410_CG_400: X410_IP build/usrp_x410_fpga_CG_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,CG_400)
##
##Experimental Targets
##-------------|-----------|----------------|----------------|------------
##Target | Bandwidth | QSFP0 | QSFP1 | DRAM
##-------------|-----------|----------------|----------------|------------
##X410_X4C_100 | 100 | 4 x 10 GbE | 100GbE | None
##X410_C1_100 | 100 | 100 GbE | None | 64b x 4 Ch
##X410_X4C_200 | 200 | 4 x 10 GbE | 100GbE | None
##X410_C1_200 | 200 | 100 GbE | None | 64b x 4 Ch
##-------------|-----------|-----------------|-----------------|------------
##Target | Bandwidth | QSFP0 | QSFP1 | DRAM
##-------------|-----------|-----------------|-----------------|------------
##X410_CG_200 | 200 | 100 GbE | 100 GbE | 64b x 4 Ch
X410_X4C_100: X410_IP build/usrp_x410_fpga_X4C_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
$(call post_build,X410,X4C_100)
X410_C1_100: X410_IP build/usrp_x410_fpga_CG_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
$(call post_build,X410,CG_100)
X410_C1_200: X410_IP build/usrp_x410_fpga_CG_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
X410_CG_200: X410_IP build/usrp_x410_fpga_CG_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
$(call post_build,X410,CG_200)
X410_X4C_200: X410_IP build/usrp_x410_fpga_X4C_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X4C_200)
##
##Other Make Targets
##------------------
.DEFAULT_GOAL := all
all: X410_X4_200 X410_CG_400 ##(Default targets)
all: X410_X4_200 X410_CG_400 X410_UC_200 ##(Default targets)
X410_IP: ##Build IP only.
+$(call vivado_ip,X410,$(DEFS) X410=1)
top/x400/dts/usrp_x410_fpga_UC.dts
+20
View File
@@ -0,0 +1,20 @@
/*
* Copyright 2023 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
/dts-v1/;
/plugin/;
#include "x410-version-info.dtsi"
#include "x410-fpga.dtsi"
#include "x410-common.dtsi"
#include "x410-rfdc.dtsi"
#include "x410-dma.dtsi"
#include "x410-100gbe-port1.dtsi"
top/x400/x410_cg_200_rfnoc_image_core.yml
+162
View File
@@ -0,0 +1,162 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Ettus Research, A National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 256 # Default bit width to use for CHDR buses
device: 'x410' # USRP type
image_core_name: 'x410_cg_200' # Name to use for the RFNoC Image Core files
default_target: 'X410_UC_200' # Default make target
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
chdr_width: 256 # Bit width of CHDR bus connection to crossbar
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 262144 # Ingress buffer size for data
ep1:
chdr_width: 256
ctrl: False
data: True
buff_size_bytes: 262144
ep2:
chdr_width: 256
ctrl: False
data: True
buff_size_bytes: 262144
ep3:
chdr_width: 256
ctrl: False
data: True
buff_size_bytes: 262144
ep4:
chdr_width: 64
ctrl: False
data: True
buff_size_bytes: 32768
ep5:
chdr_width: 64
ctrl: False
data: True
buff_size_bytes: 32768
ep6:
chdr_width: 64
ctrl: False
data: True
buff_size_bytes: 32768
ep7:
chdr_width: 64
ctrl: False
data: True
buff_size_bytes: 32768
# A list of all NoC blocks in design
# ----------------------------------
block_chdr_width: 64 # Bit width of the CHDR bus between blocks
noc_blocks:
duc0: # NoC block name
block_desc: 'duc.yml' # Block device descriptor file
parameters:
NUM_PORTS: 2
ddc0:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
duc1:
block_desc: 'duc.yml'
parameters:
NUM_PORTS: 2
ddc1:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 4
MEM_DATA_W: 64
MEM_ADDR_W: 32
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A:0 TX
- { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
# RF A:0 RX
- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
# RF A:1 TX
- { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 }
- { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
# RF A:1 RX
- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
# RF B:0 TX
- { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
- { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
# RF B:0 RX
- { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
- { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
# RF B:1 TX
- { srcblk: ep3, srcport: out0, dstblk: duc1, dstport: in_1 }
- { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 }
# RF B:1 RX
- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
- { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
# Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
- { srcblk: ep6, srcport: out0, dstblk: replay0, dstport: in_2 }
- { srcblk: replay0, srcport: out_2, dstblk: ep6, dstport: in0 }
- { srcblk: ep7, srcport: out0, dstblk: replay0, dstport: in_3 }
- { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 }
#
# BSP Connections
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio_2x, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: radio_2x, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: radio_2x, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: radio_2x, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
top/x400/x410_x4c_200_rfnoc_image_core.yml
+124
View File
@@ -0,0 +1,124 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Ettus Research, A National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 256 # Default bit width to use for CHDR buses
device: 'x410' # USRP type
image_core_name: 'x410_x4c_200' # Name to use for the RFNoC Image Core files
default_target: 'X410_X4C_200' # Default make target
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
chdr_width: 256 # Bit width of CHDR bus connection to crossbar
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 262144 # Ingress buffer size for data
ep1:
chdr_width: 256
ctrl: False
data: True
buff_size_bytes: 262144
ep2:
chdr_width: 256
ctrl: False
data: True
buff_size_bytes: 262144
ep3:
chdr_width: 256
ctrl: False
data: True
buff_size_bytes: 262144
# A list of all NoC blocks in design
# ----------------------------------
block_chdr_width: 64 # Bit width of the CHDR bus between blocks
noc_blocks:
duc0: # NoC block name
block_desc: 'duc.yml' # Block device descriptor file
parameters:
NUM_PORTS: 2
ddc0:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
duc1:
block_desc: 'duc.yml'
parameters:
NUM_PORTS: 2
ddc1:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A:0 TX
- { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
# RF A:0 RX
- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
# RF A:1 TX
- { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 }
- { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
# RF A:1 RX
- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
# RF B:0 TX
- { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
- { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
# RF B:0 RX
- { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
- { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
# RF B:1 TX
- { srcblk: ep3, srcport: out0, dstblk: duc1, dstport: in_1 }
- { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 }
# RF B:1 RX
- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
- { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
# BSP Connections
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio_2x, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: radio_2x, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: radio_2x, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: radio_2x, dstblk: ddc1, dstport: ce }