rfnoc: lib: introduce ctrl-port interface and BFM
Original-commit: 886cf97ad5d494b20c6fff0a53113f6096d458c7
This commit is contained in:
Max Köhler
@@ -1,5 +1,5 @@
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#
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# Copyright 2018 Ettus Research, A National Instruments Company
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# Copyright 2024 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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@@ -15,8 +15,9 @@ ctrlport.vh \
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))
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RFNOC_CORE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/core/, \
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rfnoc_chdr_utils_pkg.sv \
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ctrlport_pkg.sv \
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ctrlport_if.sv \
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rfnoc_chdr_utils_pkg.sv \
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axis_ctrl_endpoint.v \
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axis_ctrl_master.v \
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axis_ctrl_slave.v \
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@@ -0,0 +1,42 @@
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//
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// Copyright 2024 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Interface: ctrlport_if
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//
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// Description:
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//
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// Defines a SystemVerilog interface for the control-port bus.
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//
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interface ctrlport_if (
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input logic clk,
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input logic rst = 1'b0
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);
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import ctrlport_pkg::*;
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// Consisting of a request and a response moving in different directions.
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ctrlport_request_t req;
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ctrlport_response_t resp;
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// Master driving the request and consuming the response.
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modport master (
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input clk,
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input rst,
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output req,
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input resp
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);
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// Slave consuming the request and driving the response.
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modport slave (
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input clk,
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input rst,
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input req,
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output resp
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);
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endinterface : ctrlport_if
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@@ -14,4 +14,34 @@ package ctrlport_pkg;
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`include "ctrlport.vh"
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// typedef for status
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typedef enum logic [1:0] {
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STS_OKAY = CTRL_STS_OKAY,
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STS_CMDERR = CTRL_STS_CMDERR,
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STS_TSERR = CTRL_STS_TSERR,
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STS_WARNING = CTRL_STS_WARNING } ctrlport_status_t;
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// Defining signals as defined in Table 18 of RFNoC Specification v.1.0.1.
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// request related signals
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typedef struct packed {
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logic wr;
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logic rd;
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logic [ CTRLPORT_ADDR_W-1:0] addr;
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logic [ CTRLPORT_PORTID_W-1:0] port_id;
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logic [CTRLPORT_REM_EPID_W-1:0] remote_epid;
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logic [ CTRLPORT_PORTID_W-1:0] remote_portid;
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logic [ CTRLPORT_DATA_W-1:0] data;
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logic [ CTRLPORT_BYTE_EN_W-1:0] byte_en;
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logic has_time;
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// signal time - renamed to timestamp to avoid conflict with SystemVerilog keyword time
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logic [ CTRLPORT_TIME_W-1:0] timestamp;
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} ctrlport_request_t;
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// response related signals
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typedef struct packed {
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logic ack;
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ctrlport_status_t status;
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logic [CTRLPORT_DATA_W-1:0] data;
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} ctrlport_response_t;
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endpackage : ctrlport_pkg
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@@ -31,4 +31,10 @@ noc_shell_generic_ctrlport_pyld_chdr.v \
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timekeeper.v \
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ctrlport_terminator.v \
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chdr_strip_header.sv \
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ctrlport_if_clk_cross.sv \
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ctrlport_if_combiner.sv \
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ctrlport_if_decoder.sv \
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ctrlport_if_splitter.sv \
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ctrlport_if_terminator.sv \
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ctrlport_if_window.sv \
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))
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@@ -0,0 +1,84 @@
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//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_if_clk_cross
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//
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// Description:
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//
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// Crosses control-port interface between different clock domains.
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//
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module ctrlport_if_clk_cross
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(
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ctrlport_if.slave s_ctrlport,
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ctrlport_if.master m_ctrlport
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);
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import ctrlport_pkg::*;
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//---------------------------------------------------------------------------
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// Slave to Master Clock Crossing (Request)
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//---------------------------------------------------------------------------
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ctrlport_request_t m_req_hs;
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logic m_req_hs_valid;
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// Busy flag can be ignored as the response handshake takes at least the same
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// amount of cycles to transfer the response as this handshake instance needs
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// to release the busy flag as they are configured with the same amount of
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// synchronization stages. Furthermore the ctrlport protocol just allows for
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// one transaction to be active at the same time. A request can only be issued
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// once the response is provided.
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handshake #(
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.WIDTH($bits(ctrlport_request_t))
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) req_handshake_inst (
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.clk_a(s_ctrlport.clk),
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.rst_a(s_ctrlport.rst),
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.valid_a((s_ctrlport.req.rd | s_ctrlport.req.wr) & ~s_ctrlport.rst),
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.data_a(s_ctrlport.req),
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.busy_a(),
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.clk_b(m_ctrlport.clk),
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.valid_b(m_req_hs_valid),
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.data_b(m_req_hs)
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);
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always_comb begin
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m_ctrlport.req = m_req_hs;
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// mask read and write flags
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m_ctrlport.req.wr = m_req_hs.wr & m_req_hs_valid & ~m_ctrlport.rst;
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m_ctrlport.req.rd = m_req_hs.rd & m_req_hs_valid & ~m_ctrlport.rst;
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end
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//---------------------------------------------------------------------------
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// Master to Slave Clock Crossing (Response)
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//---------------------------------------------------------------------------
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ctrlport_response_t s_resp_hs;
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logic s_resp_hs_valid;
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// Busy flag can be ignored as the request handshake takes at least the same
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// amount of cycles to transfer the request as this handshake instance needs
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// to release the busy flag as they are configured with the same amount of
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// synchronization stages. Furthermore the ctrlport protocol just allows for
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// one transaction to be active at the same time. A response can only be
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// issued once the request is available.
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handshake #(
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.WIDTH($bits(ctrlport_response_t))
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) resp_handshake_inst (
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.clk_a(m_ctrlport.clk),
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.rst_a(m_ctrlport.rst),
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.valid_a(m_ctrlport.resp.ack & ~m_ctrlport.rst),
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.data_a(m_ctrlport.resp),
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.busy_a(),
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.clk_b(s_ctrlport.clk),
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.valid_b(s_resp_hs_valid),
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.data_b(s_resp_hs)
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);
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always_comb begin
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s_ctrlport.resp = s_resp_hs;
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s_ctrlport.resp.ack = s_resp_hs.ack & s_resp_hs_valid & ~s_ctrlport.rst;
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end
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endmodule
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@@ -0,0 +1,242 @@
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//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_if_combiner
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//
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// Description:
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//
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// This block is an arbiter that merges control-port interfaces. This block is
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// used when you have multiple control-port masters that need to access a
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// single slave. For example, a NoC block with multiple submodules that each
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// need to read and/or write registers outside of themselves.
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//
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// This module combines the control-port requests from multiple masters into a
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// single request for one slave. Simultaneous requests are handled in the order
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// specified by PRIORITY. The responding ACK is routed back to the requester.
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//
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// The module has been designed so that the latency through it is always the
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// same when PRIORITY=1 and there is no contention, so that it can be used in
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// applications where deterministic behavior is desired.
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//
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// Parameters:
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//
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// NUM_MASTERS : The number of control-port masters to connect to a single
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// control-port slave.
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// PRIORITY : Use PRIORITY = 0 for round robin arbitration, PRIORITY = 1
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// for priority arbitration (lowest number port serviced first).
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// TIMEOUT : Number of cycles to wait for a response before aborting the wait for an ack.
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// TIMEOUT = 0 will not add a timeout.
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//
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module ctrlport_if_combiner #(
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int NUM_MASTERS = 2,
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bit PRIORITY = 0,
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int TIMEOUT = 0
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) (
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// Slave Interfaces
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ctrlport_if.slave s_ctrlport [NUM_MASTERS-1:0],
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// Master Interface
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ctrlport_if.master m_ctrlport
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);
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import ctrlport_pkg::*;
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logic [$clog2(NUM_MASTERS)-1:0] slave_sel = '0; // Tracks which slave port is
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// currently being serviced.
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logic req_load_output = '0;
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logic timeout_occurred = '0;
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// Helper function to convert one hot vector to binary index
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// (LSB = index 0)
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function integer one_hot_to_binary(input [NUM_MASTERS-1:0] one_hot_vec);
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integer i, total;
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begin
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total = 0;
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for (i = 0; i < NUM_MASTERS; i++) begin
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if (one_hot_vec[i]) begin
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total = total + i;
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end
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end
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one_hot_to_binary = total;
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end
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endfunction
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//---------------------------------------------------------------------------
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// Input Registers
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//---------------------------------------------------------------------------
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//
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// Latch each request until it can be serviced. Only one request per slave
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// can be in progress at a time.
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//
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//---------------------------------------------------------------------------
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ctrlport_request_t req_buffer [NUM_MASTERS-1:0];
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logic [NUM_MASTERS-1:0] req_valid;
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for (genvar i = 0; i < NUM_MASTERS; i++) begin : gen_input_regs
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always_ff @(posedge m_ctrlport.clk) begin
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if (m_ctrlport.rst) begin
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req_valid[i] <= '0;
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end else begin
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if (s_ctrlport[i].req.wr | s_ctrlport[i].req.rd) begin
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// Mark this slave's request valid and save the request information
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req_valid[i] <= '1;
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end
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// Clear the active request when it gets output
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if (req_load_output && (i == slave_sel)) begin
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req_valid[i] <= '0;
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end
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end
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// Save buffer without reset
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if (s_ctrlport[i].req.wr | s_ctrlport[i].req.rd) begin
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req_buffer[i] <= s_ctrlport[i].req;
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end
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end
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end
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//---------------------------------------------------------------------------
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// Arbitration State Machine
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//---------------------------------------------------------------------------
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//
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// This state machine tracks which slave port is being serviced and which to
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// service next. This is done using a counter that simply checks each port in
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// sequential order and then stops when it finds one that has a valid request.
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//
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//---------------------------------------------------------------------------
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logic req_active = '0; // Indicates if there's a request being serviced
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logic [NUM_MASTERS-1:0] next_slave_one_hot; // one hot for next active request
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// (used for PRIORITY = 1)
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for (genvar i = 0; i < NUM_MASTERS; i++) begin : gen_next_slave_one_hot
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if (i == 0) begin
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assign next_slave_one_hot[i] = req_valid[i];
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end else begin
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assign next_slave_one_hot[i] = req_valid[i] & ~next_slave_one_hot[i-1];
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end
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end
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always_ff @(posedge m_ctrlport.clk) begin
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if (m_ctrlport.rst) begin
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slave_sel <= '0;
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req_active <= '0;
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req_load_output <= '0;
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end else begin
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req_load_output <= '0;
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if (req_active) begin
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// Wait until we get the response before we allow another request
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if (m_ctrlport.resp.ack || timeout_occurred) begin
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req_active <= '0;
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// Go to next slave immediately
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if(PRIORITY == 1)
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slave_sel <= one_hot_to_binary(next_slave_one_hot);
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// Round robin - Go to the next slave so we don't service the same
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// slave again
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else if(slave_sel == NUM_MASTERS-1)
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slave_sel <= '0;
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else
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slave_sel <= slave_sel + 1;
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end
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end else begin
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// No active request in progress, so check if there's a new request on
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// the selected slave.
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if (req_valid[slave_sel]) begin
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req_active <= '1;
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req_load_output <= '1;
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end else begin
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// Go to next slave immediately
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if(PRIORITY == 1)
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slave_sel <= one_hot_to_binary(next_slave_one_hot);
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// Round robin - Nothing from this slave, so move to the next slave.
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else if (slave_sel == NUM_MASTERS-1)
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slave_sel <= '0;
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else
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slave_sel <= slave_sel + 1;
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end
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end
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end
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end
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//---------------------------------------------------------------------------
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// Output Register
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//---------------------------------------------------------------------------
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//
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// Here we load the active request for a single clock cycle and demultiplex
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// the response back to the requesting master.
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//
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//---------------------------------------------------------------------------
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always_ff @(posedge m_ctrlport.clk) begin
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// Load the active request
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if (req_load_output) begin
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m_ctrlport.req <= req_buffer[slave_sel];
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end else begin
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m_ctrlport.req.wr <= '0;
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m_ctrlport.req.rd <= '0;
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end
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if (m_ctrlport.rst) begin
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// only reset the flags of the master interface
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m_ctrlport.req.wr <= '0;
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m_ctrlport.req.rd <= '0;
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end
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end
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// Output any response to the master that made the request
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for (genvar i = 0; i < NUM_MASTERS; i++) begin : gen_output_regs
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always_ff @(posedge m_ctrlport.clk) begin
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// Give the response data to all the slaves (no demux, to save logic)
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s_ctrlport[i].resp <= m_ctrlport.resp;
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// Give the ack only to the master that made the request (use a demux)
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if (m_ctrlport.rst) begin
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s_ctrlport[i].resp.ack <= '0;
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end else if (i == slave_sel && m_ctrlport.resp.ack) begin
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s_ctrlport[i].resp.ack <= '1;
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end else begin
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s_ctrlport[i].resp.ack <= '0;
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end
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end
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end
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//---------------------------------------------------------------------------
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// optional watchdog
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//---------------------------------------------------------------------------
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if (TIMEOUT == 0) begin: gen_no_timeout
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// never set a timeout but in always_ff block to avoid error with synchronous assignment
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// in gen_timeout block below
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always_ff @(posedge m_ctrlport.clk) begin
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timeout_occurred = '0;
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end
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end else begin: gen_timeout
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// When the timeout occurred it takes 2 more clock cycles for the counter to reach zero
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// The path is: timeout_occurred -> req_active = 0 -> timeout_counter = 0
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// As the timeout counter has a minimum width of 2 bits the counter cannot reach TIMEOUT+1
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// again within these two clock cycles.
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// Therefore no other reset other than req_active is needed on this signal.
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logic [$clog2(TIMEOUT+2):0] timeout_counter = '0;
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// Reset the timeout counter when there is no active request
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always_ff @(posedge m_ctrlport.clk) begin
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if (~req_active) begin
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timeout_counter <= '0;
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end else begin
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timeout_counter <= timeout_counter + 1;
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end
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// Set the timeout flag for one cycle when the counter reaches the timeout value.
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// The delay of the additional register compensates the delay of the logic above to
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// load the active request into the output register.
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timeout_occurred <= timeout_counter == TIMEOUT;
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end
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end
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endmodule
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@@ -0,0 +1,107 @@
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//
|
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// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
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// Module: ctrlport_if_decoder
|
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//
|
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// Description:
|
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//
|
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// This block splits a single control port interface into multiple. It is
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// used when you have a single master that needs to access multiple slaves.
|
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//
|
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// This version also implements address decoding. The request is passed to a
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// slave only if the address falls within that slave's address space. Each
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// slave can have a unique base address and address space size.
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//
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// When passed to the slave, the base address is subtracted from the request
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// address.
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//
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// Parameters:
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//
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// NUM_SLAVES : The number of slaves to connect to a master.
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// PORT_BASE : Base addresses to use for each slave.
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// PORT_SIZE : Size of the address space for each slave.
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//
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module ctrlport_if_decoder #(
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int NUM_SLAVES = 2,
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int PORT_BASE [NUM_SLAVES] = '{'h0, 'h100},
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int PORT_SIZE [NUM_SLAVES] = '{'h100, 'h100}
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) (
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// Slave Interface
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ctrlport_if.slave s_ctrlport,
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// Master Interfaces
|
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ctrlport_if.master m_ctrlport [NUM_SLAVES]
|
||||
);
|
||||
|
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import ctrlport_pkg::*;
|
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|
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//---------------------------------------------------------------------------
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||||
// Check the address ranges
|
||||
//---------------------------------------------------------------------------
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||||
for (genvar i = 0; i < NUM_SLAVES; i = i+1) begin : gen_overlap_1
|
||||
for (genvar j = 0; j < NUM_SLAVES; j = j+1) begin : gen_overlap_2
|
||||
if (i != j) begin
|
||||
if ((PORT_BASE[i] >= PORT_BASE[j]) &&
|
||||
(PORT_BASE[i] < PORT_BASE[j] + PORT_SIZE[j])) begin
|
||||
$error("Port %0d overlaps with port %0d.", i, j);
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Split the requests among the slaves
|
||||
//---------------------------------------------------------------------------
|
||||
for (genvar i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
|
||||
always_ff @(posedge s_ctrlport.clk) begin
|
||||
// unconditionally pass the request by default
|
||||
m_ctrlport[i].req <= s_ctrlport.req;
|
||||
// pass only the respective address bits
|
||||
m_ctrlport[i].req.addr <= '0;
|
||||
m_ctrlport[i].req.addr[$clog2(PORT_SIZE[i])-1:0] <= s_ctrlport.req.addr - PORT_BASE[i];
|
||||
|
||||
// read and write trigger transactions and therefore need to react to reset
|
||||
if (s_ctrlport.rst) begin
|
||||
m_ctrlport[i].req.wr <= 1'b0;
|
||||
m_ctrlport[i].req.rd <= 1'b0;
|
||||
end else begin
|
||||
automatic logic address_in_range;
|
||||
address_in_range = (s_ctrlport.req.addr >= PORT_BASE[i]) &&
|
||||
(s_ctrlport.req.addr < PORT_BASE[i] + PORT_SIZE[i]);
|
||||
m_ctrlport[i].req.wr <= s_ctrlport.req.wr & address_in_range;
|
||||
m_ctrlport[i].req.rd <= s_ctrlport.req.rd & address_in_range;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Decode the responses
|
||||
//---------------------------------------------------------------------------
|
||||
// Take the responses and mask them with their respective ack
|
||||
ctrlport_response_t masked_resp [NUM_SLAVES-1:0];
|
||||
for (genvar i = 0; i < NUM_SLAVES; i++) begin : gen_mask
|
||||
assign masked_resp[i] = m_ctrlport[i].resp.ack ? m_ctrlport[i].resp : '0;
|
||||
end
|
||||
|
||||
// Combine the masked responses by OR'ing them together
|
||||
ctrlport_response_t combined_resp;
|
||||
always_comb begin : response_combine
|
||||
combined_resp = '0;
|
||||
for (int i = 0; i < NUM_SLAVES; i++) begin : gen_or
|
||||
combined_resp = combined_resp | masked_resp[i];
|
||||
end
|
||||
end
|
||||
|
||||
// Register the output to break combinatorial path
|
||||
always_ff @(posedge s_ctrlport.clk) begin : response_reg
|
||||
s_ctrlport.resp <= combined_resp;
|
||||
|
||||
if (s_ctrlport.rst) begin
|
||||
s_ctrlport.resp.ack <= '0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,85 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_if_splitter
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This block splits a single control-port interface into multiple. It is used
|
||||
// when you have a single master that needs to access multiple slaves. For
|
||||
// example, a NoC block where the registers are implemented in multiple
|
||||
// submodules that must be read/written by a single NoC shell.
|
||||
//
|
||||
// Note that this block does not do any address decoding, so the connected
|
||||
// slaves must use non-overlapping address spaces.
|
||||
//
|
||||
// This module takes the request received by its single slave interface and
|
||||
// outputs it on all its master interfaces. In the opposite direction, it takes
|
||||
// the responses received by its multiple master interfaces and combines them
|
||||
// into a single response on its slave interface. This is done by using the ack
|
||||
// bit of each response to mask the other bits of the response, then OR'ing all
|
||||
// of the masked responses together onto a single response bus. This is valid
|
||||
// because only one block is allowed to respond to a single request.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// NUM_SLAVES : The number of slaves you want to connect to a master.
|
||||
//
|
||||
|
||||
|
||||
module ctrlport_if_splitter #(
|
||||
int NUM_SLAVES = 2
|
||||
) (
|
||||
// Slave Interface
|
||||
ctrlport_if.slave s_ctrlport,
|
||||
// Master Interfaces
|
||||
ctrlport_if.master m_ctrlport [NUM_SLAVES-1:0]
|
||||
);
|
||||
|
||||
import ctrlport_pkg::*;
|
||||
|
||||
generate
|
||||
if (NUM_SLAVES == 1) begin : gen_no_split
|
||||
assign m_ctrlport[0].req = s_ctrlport.req;
|
||||
assign s_ctrlport.resp = m_ctrlport[0].resp;
|
||||
end else begin : gen_splitter
|
||||
//---------------------------------------------------------------------------
|
||||
// Split the requests among the slaves
|
||||
//---------------------------------------------------------------------------
|
||||
for (genvar i = 0; i < NUM_SLAVES; i++) begin : gen_split
|
||||
// No special logic is required to split the requests from the master among
|
||||
// multiple slaves.
|
||||
assign m_ctrlport[i].req = s_ctrlport.req;
|
||||
end
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Decode the responses
|
||||
//---------------------------------------------------------------------------
|
||||
// Take the responses and mask them with their respective ack
|
||||
ctrlport_response_t masked_resp [NUM_SLAVES-1:0];
|
||||
for (genvar i = 0; i < NUM_SLAVES; i++) begin : gen_mask
|
||||
assign masked_resp[i] = m_ctrlport[i].resp.ack ? m_ctrlport[i].resp : '0;
|
||||
end
|
||||
|
||||
// Combine the masked responses by OR'ing them together
|
||||
ctrlport_response_t combined_resp;
|
||||
always_comb begin : response_combine
|
||||
combined_resp = '0;
|
||||
for (int i = 0; i < NUM_SLAVES; i++) begin : gen_or
|
||||
combined_resp = combined_resp | masked_resp[i];
|
||||
end
|
||||
end
|
||||
|
||||
// Register the output to break combinatorial path
|
||||
always_ff @(posedge s_ctrlport.clk) begin : response_reg
|
||||
s_ctrlport.resp <= combined_resp;
|
||||
|
||||
if (s_ctrlport.rst) begin
|
||||
s_ctrlport.resp.ack <= '0;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
@@ -0,0 +1,44 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_if_terminator
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// Returns an error for all ctrlport requests in given address range.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// BASE_ADDRESS : First address to generate response for.
|
||||
// WINDOW_SIZE : Size of the address space.
|
||||
// Last address in range will be BASE_ADDRESS + WINDOW_SIZE - 1.
|
||||
//
|
||||
|
||||
module ctrlport_if_terminator #(
|
||||
int BASE_ADDRESS = 0,
|
||||
int WINDOW_SIZE = 32
|
||||
)(
|
||||
ctrlport_if.slave s_ctrlport
|
||||
);
|
||||
|
||||
import ctrlport_pkg::*;
|
||||
|
||||
// drive acknowledgement on requests but not on reset
|
||||
always_ff @(posedge s_ctrlport.clk) begin
|
||||
if (s_ctrlport.rst) begin
|
||||
s_ctrlport.resp.ack <= 1'b0;
|
||||
end else if ((s_ctrlport.req.addr >= BASE_ADDRESS) &&
|
||||
(s_ctrlport.req.addr < BASE_ADDRESS + WINDOW_SIZE)) begin
|
||||
s_ctrlport.resp.ack <= s_ctrlport.req.wr | s_ctrlport.req.rd;
|
||||
end else begin
|
||||
s_ctrlport.resp.ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// other outputs are fixed
|
||||
assign s_ctrlport.resp.status = STS_CMDERR;
|
||||
assign s_ctrlport.resp.data = '0;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,45 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_if_window
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// Copy requests from slave to master interface when s_ctrlport_req_addr is in
|
||||
// address range specified by the parameters.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// BASE_ADDRESS : Base address of the window.
|
||||
// This will be the first address in the range.
|
||||
// WINDOW_SIZE : Size of the address space for the window.
|
||||
// Last address in range will be BASE_ADDRESS + WINDOW_SIZE - 1.
|
||||
//
|
||||
|
||||
module ctrlport_if_window #(
|
||||
int BASE_ADDRESS = 0,
|
||||
int WINDOW_SIZE = 32
|
||||
) (
|
||||
ctrlport_if.slave s_ctrlport,
|
||||
ctrlport_if.master m_ctrlport
|
||||
);
|
||||
|
||||
always_comb begin
|
||||
// Mask write and read flag
|
||||
automatic logic address_in_range = (s_ctrlport.req.addr >= BASE_ADDRESS) &&
|
||||
(s_ctrlport.req.addr < BASE_ADDRESS + WINDOW_SIZE);
|
||||
|
||||
// initialize master request by slave request
|
||||
m_ctrlport.req = s_ctrlport.req;
|
||||
|
||||
// overwrite write and read flag with in range flag
|
||||
m_ctrlport.req.wr = s_ctrlport.req.wr && address_in_range;
|
||||
m_ctrlport.req.rd = s_ctrlport.req.rd && address_in_range;
|
||||
|
||||
// transfer reponse without change
|
||||
s_ctrlport.resp = m_ctrlport.resp;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -5,17 +5,18 @@
|
||||
#
|
||||
|
||||
##################################################
|
||||
# Dependencies for AXI BFMS
|
||||
# Dependencies for BFMs
|
||||
##################################################
|
||||
|
||||
SIM_RFNOC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/, \
|
||||
axi4lite_sv/PkgAxiLite.sv \
|
||||
axi4lite_sv/AxiLiteIf.sv \
|
||||
axi4s_sv/AxiStreamIf.sv \
|
||||
rfnoc/core/ctrlport_pkg.sv \
|
||||
))
|
||||
|
||||
##################################################
|
||||
# Simulation Libraries/Headers for AXI based interfaces
|
||||
# Simulation Libraries/Headers for various interfaces
|
||||
##################################################
|
||||
|
||||
SIM_RFNOC_SRCS += $(abspath $(addprefix $(BASE_DIR)/../sim/rfnoc/, \
|
||||
@@ -33,4 +34,5 @@ PkgRfnocItemUtils.sv \
|
||||
PkgCtrlIfaceBfm.sv \
|
||||
PkgChdrIfaceBfm.sv \
|
||||
PkgRfnocBlockCtrlBfm.sv \
|
||||
ctrlport_bfm_pkg.sv \
|
||||
))
|
||||
|
||||
@@ -0,0 +1,231 @@
|
||||
//
|
||||
// Copyright 2024 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Package: ctrlport_bfm_pkg
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// Package defining a Control Port bus functional model (BFM).
|
||||
// See the RFNoC Specification for a protocol description.
|
||||
//
|
||||
|
||||
package ctrlport_bfm_pkg;
|
||||
|
||||
import ctrlport_pkg::*;
|
||||
|
||||
class ctrlport_bfm;
|
||||
|
||||
// create combined request and response struct for mailbox
|
||||
typedef struct {
|
||||
ctrlport_request_t req;
|
||||
ctrlport_response_t resp;
|
||||
bit skip_data_check;
|
||||
} ctrlport_transfer_t;
|
||||
|
||||
local mailbox #(ctrlport_transfer_t) transactions;
|
||||
|
||||
// link to interface
|
||||
local virtual ctrlport_if iface;
|
||||
|
||||
// data copy for response data
|
||||
local logic [CTRLPORT_DATA_W-1:0] reponse_data;
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
// Constructor
|
||||
// ------------------------------------------------------------------
|
||||
// Class constructor. This must be given an interface for the master
|
||||
// connection and an interface for the slave connection.
|
||||
function new(virtual ctrlport_if iface);
|
||||
this.iface = iface;
|
||||
transactions = new;
|
||||
endfunction
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
// Asynchronous transaction handling
|
||||
// ------------------------------------------------------------------
|
||||
// Queue an asynchronous transaction (read or write with full request)
|
||||
task async_request(
|
||||
ctrlport_request_t request,
|
||||
ctrlport_response_t expected_response,
|
||||
bit skip_data_check = '0
|
||||
);
|
||||
assert (request.rd || request.wr) else $error(1, "Transaction must be read or write");
|
||||
transactions.put('{request, expected_response, skip_data_check});
|
||||
endtask
|
||||
|
||||
// Queue a simple write transaction
|
||||
task async_write(
|
||||
logic[CTRLPORT_ADDR_W-1:0] addr,
|
||||
logic[CTRLPORT_DATA_W-1:0] data,
|
||||
ctrlport_status_t expected_status = STS_OKAY
|
||||
);
|
||||
ctrlport_request_t request;
|
||||
ctrlport_response_t response;
|
||||
|
||||
request = '0;
|
||||
request.wr = '1;
|
||||
request.addr = addr;
|
||||
request.data = data;
|
||||
|
||||
response = '0;
|
||||
response.status = expected_status;
|
||||
|
||||
async_request(request, response);
|
||||
endtask;
|
||||
|
||||
// Queue a simple read transaction with automated response checking
|
||||
task async_read(
|
||||
logic [CTRLPORT_ADDR_W-1:0] addr,
|
||||
logic [CTRLPORT_DATA_W-1:0] expected_data,
|
||||
ctrlport_status_t expected_status = STS_OKAY
|
||||
);
|
||||
ctrlport_request_t request;
|
||||
ctrlport_response_t response;
|
||||
|
||||
request = '0;
|
||||
request.rd = '1;
|
||||
request.addr = addr;
|
||||
|
||||
response = '0;
|
||||
response.status = expected_status;
|
||||
response.data = expected_data;
|
||||
|
||||
async_request(request, response);
|
||||
endtask;
|
||||
|
||||
// wait for all transactions to be processed
|
||||
task wait_complete();
|
||||
while(transactions.num() > 0) begin
|
||||
@(posedge iface.clk);
|
||||
end
|
||||
endtask
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
// Synchronous transaction handling
|
||||
// ------------------------------------------------------------------
|
||||
// Perform a request and get response
|
||||
task request(
|
||||
input ctrlport_request_t request,
|
||||
input ctrlport_response_t expected_response,
|
||||
output logic[CTRLPORT_DATA_W-1:0] data
|
||||
);
|
||||
async_request(request, expected_response);
|
||||
wait_complete();
|
||||
data = reponse_data;
|
||||
endtask;
|
||||
|
||||
// Perform a simple write transaction
|
||||
task write(
|
||||
logic[CTRLPORT_ADDR_W-1:0] addr,
|
||||
logic[CTRLPORT_DATA_W-1:0] data,
|
||||
ctrlport_status_t expected_status = STS_OKAY
|
||||
);
|
||||
async_write(addr, data, expected_status);
|
||||
wait_complete();
|
||||
endtask;
|
||||
|
||||
// Perform a simple read transaction, no response data check, return data from interface
|
||||
task read(
|
||||
input logic[CTRLPORT_ADDR_W-1:0] addr,
|
||||
output logic[CTRLPORT_DATA_W-1:0] data,
|
||||
input ctrlport_status_t expected_status = STS_OKAY
|
||||
);
|
||||
ctrlport_request_t request;
|
||||
ctrlport_response_t response;
|
||||
|
||||
request = '0;
|
||||
request.rd = '1;
|
||||
request.addr = addr;
|
||||
|
||||
response = '0;
|
||||
response.status = expected_status;
|
||||
|
||||
async_request(request, response, '1);
|
||||
wait_complete();
|
||||
data = reponse_data;
|
||||
endtask;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
// Signal handling
|
||||
// ------------------------------------------------------------------
|
||||
// Start the BFM.
|
||||
// This will join a separate thread for the interface handling.
|
||||
task run();
|
||||
fork
|
||||
request_body();
|
||||
join_none
|
||||
endtask
|
||||
|
||||
// Control the master request interface
|
||||
local task request_body();
|
||||
ctrlport_transfer_t transfer;
|
||||
ctrlport_request_t request_idle;
|
||||
|
||||
// initialize request interface
|
||||
request_idle = 'x;
|
||||
request_idle.wr = '0;
|
||||
request_idle.rd = '0;
|
||||
iface.req = request_idle;
|
||||
|
||||
// ignore first clock cycle to let response settle
|
||||
@(posedge iface.clk);
|
||||
|
||||
forever begin
|
||||
// handle any available transaction (but leave it in the mailbox for now)
|
||||
if (transactions.try_peek(transfer)) begin
|
||||
// wait for reset to be deasserted
|
||||
while(iface.rst) begin
|
||||
@(posedge iface.clk);
|
||||
check_no_response();
|
||||
end
|
||||
|
||||
// send request
|
||||
iface.req = transfer.req;
|
||||
// check minimum time for response on interface
|
||||
@(negedge iface.clk);
|
||||
check_no_response();
|
||||
|
||||
// reset request interface
|
||||
@(posedge iface.clk);
|
||||
iface.req = request_idle;
|
||||
|
||||
// wait for response
|
||||
while(!iface.resp.ack) begin
|
||||
@(posedge iface.clk);
|
||||
end
|
||||
|
||||
// status is always expected to match
|
||||
assert (iface.resp.status == transfer.resp.status) else
|
||||
$error(1, "Unexpected status received on interface. Expected: %2b Received: %2b", transfer.resp.status, iface.resp.status);
|
||||
|
||||
// check data if read and data check is not skipped
|
||||
if (transfer.req.rd && !transfer.skip_data_check) begin
|
||||
assert (iface.resp.data == transfer.resp.data) else
|
||||
$error(1, "Unexpected data received on interface. Expected: %h Received: %h", transfer.resp.data, iface.resp.data);
|
||||
end
|
||||
|
||||
// save data for read operations
|
||||
reponse_data = iface.resp.data;
|
||||
|
||||
// request is done -> remove from queue
|
||||
transactions.get(transfer);
|
||||
|
||||
// wait at least one clock cycle for next check of mailbox
|
||||
end else begin
|
||||
@(posedge iface.clk);
|
||||
check_no_response();
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
// Check for no response in this clock cycle
|
||||
local task check_no_response();
|
||||
assert (iface.resp.ack == '0) else $error(1, "Unexpected response received on interface: %p", iface.resp);
|
||||
endtask
|
||||
|
||||
endclass
|
||||
|
||||
endpackage
|
||||
Reference in New Issue
Block a user