rfnoc: lib: introduce ctrl-port interface and BFM
Original-commit: 886cf97ad5d494b20c6fff0a53113f6096d458c7
This commit is contained in:
Max Köhler
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//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_if_combiner
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//
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// Description:
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//
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// This block is an arbiter that merges control-port interfaces. This block is
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// used when you have multiple control-port masters that need to access a
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// single slave. For example, a NoC block with multiple submodules that each
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// need to read and/or write registers outside of themselves.
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//
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// This module combines the control-port requests from multiple masters into a
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// single request for one slave. Simultaneous requests are handled in the order
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// specified by PRIORITY. The responding ACK is routed back to the requester.
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//
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// The module has been designed so that the latency through it is always the
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// same when PRIORITY=1 and there is no contention, so that it can be used in
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// applications where deterministic behavior is desired.
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//
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// Parameters:
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//
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// NUM_MASTERS : The number of control-port masters to connect to a single
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// control-port slave.
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// PRIORITY : Use PRIORITY = 0 for round robin arbitration, PRIORITY = 1
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// for priority arbitration (lowest number port serviced first).
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// TIMEOUT : Number of cycles to wait for a response before aborting the wait for an ack.
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// TIMEOUT = 0 will not add a timeout.
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//
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module ctrlport_if_combiner #(
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int NUM_MASTERS = 2,
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bit PRIORITY = 0,
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int TIMEOUT = 0
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) (
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// Slave Interfaces
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ctrlport_if.slave s_ctrlport [NUM_MASTERS-1:0],
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// Master Interface
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ctrlport_if.master m_ctrlport
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);
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import ctrlport_pkg::*;
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logic [$clog2(NUM_MASTERS)-1:0] slave_sel = '0; // Tracks which slave port is
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// currently being serviced.
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logic req_load_output = '0;
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logic timeout_occurred = '0;
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// Helper function to convert one hot vector to binary index
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// (LSB = index 0)
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function integer one_hot_to_binary(input [NUM_MASTERS-1:0] one_hot_vec);
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integer i, total;
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begin
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total = 0;
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for (i = 0; i < NUM_MASTERS; i++) begin
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if (one_hot_vec[i]) begin
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total = total + i;
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end
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end
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one_hot_to_binary = total;
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end
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endfunction
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//---------------------------------------------------------------------------
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// Input Registers
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//---------------------------------------------------------------------------
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//
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// Latch each request until it can be serviced. Only one request per slave
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// can be in progress at a time.
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//
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//---------------------------------------------------------------------------
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ctrlport_request_t req_buffer [NUM_MASTERS-1:0];
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logic [NUM_MASTERS-1:0] req_valid;
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for (genvar i = 0; i < NUM_MASTERS; i++) begin : gen_input_regs
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always_ff @(posedge m_ctrlport.clk) begin
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if (m_ctrlport.rst) begin
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req_valid[i] <= '0;
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end else begin
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if (s_ctrlport[i].req.wr | s_ctrlport[i].req.rd) begin
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// Mark this slave's request valid and save the request information
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req_valid[i] <= '1;
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end
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// Clear the active request when it gets output
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if (req_load_output && (i == slave_sel)) begin
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req_valid[i] <= '0;
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end
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end
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// Save buffer without reset
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if (s_ctrlport[i].req.wr | s_ctrlport[i].req.rd) begin
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req_buffer[i] <= s_ctrlport[i].req;
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end
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end
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end
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//---------------------------------------------------------------------------
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// Arbitration State Machine
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//---------------------------------------------------------------------------
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//
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// This state machine tracks which slave port is being serviced and which to
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// service next. This is done using a counter that simply checks each port in
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// sequential order and then stops when it finds one that has a valid request.
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//
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//---------------------------------------------------------------------------
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logic req_active = '0; // Indicates if there's a request being serviced
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logic [NUM_MASTERS-1:0] next_slave_one_hot; // one hot for next active request
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// (used for PRIORITY = 1)
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for (genvar i = 0; i < NUM_MASTERS; i++) begin : gen_next_slave_one_hot
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if (i == 0) begin
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assign next_slave_one_hot[i] = req_valid[i];
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end else begin
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assign next_slave_one_hot[i] = req_valid[i] & ~next_slave_one_hot[i-1];
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end
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end
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always_ff @(posedge m_ctrlport.clk) begin
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if (m_ctrlport.rst) begin
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slave_sel <= '0;
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req_active <= '0;
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req_load_output <= '0;
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end else begin
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req_load_output <= '0;
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if (req_active) begin
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// Wait until we get the response before we allow another request
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if (m_ctrlport.resp.ack || timeout_occurred) begin
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req_active <= '0;
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// Go to next slave immediately
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if(PRIORITY == 1)
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slave_sel <= one_hot_to_binary(next_slave_one_hot);
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// Round robin - Go to the next slave so we don't service the same
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// slave again
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else if(slave_sel == NUM_MASTERS-1)
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slave_sel <= '0;
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else
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slave_sel <= slave_sel + 1;
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end
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end else begin
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// No active request in progress, so check if there's a new request on
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// the selected slave.
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if (req_valid[slave_sel]) begin
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req_active <= '1;
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req_load_output <= '1;
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end else begin
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// Go to next slave immediately
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if(PRIORITY == 1)
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slave_sel <= one_hot_to_binary(next_slave_one_hot);
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// Round robin - Nothing from this slave, so move to the next slave.
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else if (slave_sel == NUM_MASTERS-1)
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slave_sel <= '0;
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else
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slave_sel <= slave_sel + 1;
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end
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end
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end
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end
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//---------------------------------------------------------------------------
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// Output Register
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//---------------------------------------------------------------------------
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//
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// Here we load the active request for a single clock cycle and demultiplex
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// the response back to the requesting master.
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//
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//---------------------------------------------------------------------------
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always_ff @(posedge m_ctrlport.clk) begin
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// Load the active request
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if (req_load_output) begin
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m_ctrlport.req <= req_buffer[slave_sel];
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end else begin
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m_ctrlport.req.wr <= '0;
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m_ctrlport.req.rd <= '0;
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end
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if (m_ctrlport.rst) begin
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// only reset the flags of the master interface
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m_ctrlport.req.wr <= '0;
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m_ctrlport.req.rd <= '0;
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end
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end
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// Output any response to the master that made the request
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for (genvar i = 0; i < NUM_MASTERS; i++) begin : gen_output_regs
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always_ff @(posedge m_ctrlport.clk) begin
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// Give the response data to all the slaves (no demux, to save logic)
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s_ctrlport[i].resp <= m_ctrlport.resp;
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// Give the ack only to the master that made the request (use a demux)
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if (m_ctrlport.rst) begin
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s_ctrlport[i].resp.ack <= '0;
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end else if (i == slave_sel && m_ctrlport.resp.ack) begin
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s_ctrlport[i].resp.ack <= '1;
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end else begin
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s_ctrlport[i].resp.ack <= '0;
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end
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end
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end
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//---------------------------------------------------------------------------
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// optional watchdog
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//---------------------------------------------------------------------------
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if (TIMEOUT == 0) begin: gen_no_timeout
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// never set a timeout but in always_ff block to avoid error with synchronous assignment
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// in gen_timeout block below
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always_ff @(posedge m_ctrlport.clk) begin
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timeout_occurred = '0;
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end
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end else begin: gen_timeout
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// When the timeout occurred it takes 2 more clock cycles for the counter to reach zero
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// The path is: timeout_occurred -> req_active = 0 -> timeout_counter = 0
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// As the timeout counter has a minimum width of 2 bits the counter cannot reach TIMEOUT+1
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// again within these two clock cycles.
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// Therefore no other reset other than req_active is needed on this signal.
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logic [$clog2(TIMEOUT+2):0] timeout_counter = '0;
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// Reset the timeout counter when there is no active request
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always_ff @(posedge m_ctrlport.clk) begin
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if (~req_active) begin
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timeout_counter <= '0;
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end else begin
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timeout_counter <= timeout_counter + 1;
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end
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// Set the timeout flag for one cycle when the counter reaches the timeout value.
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// The delay of the additional register compensates the delay of the logic above to
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// load the active request into the output register.
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timeout_occurred <= timeout_counter == TIMEOUT;
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end
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end
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endmodule
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