rfnoc: lib: introduce ctrl-port interface and BFM

Original-commit: 886cf97ad5d494b20c6fff0a53113f6096d458c7

lib/rfnoc/core/Makefile.srcs

@@ -1,5 +1,5 @@
 #
-# Copyright 2018 Ettus Research, A National Instruments Company
+# Copyright 2024 Ettus Research, a National Instruments Brand
 #
 # SPDX-License-Identifier: LGPL-3.0-or-later
 #
@@ -15,8 +15,9 @@ ctrlport.vh \
 ))
 
 RFNOC_CORE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/core/, \
-rfnoc_chdr_utils_pkg.sv \
 ctrlport_pkg.sv \
+ctrlport_if.sv \
+rfnoc_chdr_utils_pkg.sv \
 axis_ctrl_endpoint.v \
 axis_ctrl_master.v \
 axis_ctrl_slave.v \

lib/rfnoc/core/ctrlport_if.sv

@@ -0,0 +1,42 @@
+//
+// Copyright 2024 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Interface: ctrlport_if
+//
+// Description:
+//
+//   Defines a SystemVerilog interface for the control-port bus.
+//
+
+interface ctrlport_if (
+  input logic clk,
+  input logic rst = 1'b0
+);
+
+  import ctrlport_pkg::*;
+
+  // Consisting of a request and a response moving in different directions.
+  ctrlport_request_t  req;
+  ctrlport_response_t resp;
+
+  // Master driving the request and consuming the response.
+  modport master (
+    input  clk,
+    input  rst,
+
+    output req,
+    input  resp
+  );
+
+  // Slave consuming the request and driving the response.
+  modport slave (
+    input  clk,
+    input  rst,
+
+    input  req,
+    output resp
+  );
+
+endinterface : ctrlport_if

lib/rfnoc/core/ctrlport_pkg.sv

@@ -14,4 +14,34 @@ package ctrlport_pkg;
 
   `include "ctrlport.vh"
 
+  // typedef for status
+  typedef enum logic [1:0] {
+    STS_OKAY    = CTRL_STS_OKAY,
+    STS_CMDERR  = CTRL_STS_CMDERR,
+    STS_TSERR   = CTRL_STS_TSERR,
+    STS_WARNING = CTRL_STS_WARNING } ctrlport_status_t;
+
+  // Defining signals as defined in Table 18 of RFNoC Specification v.1.0.1.
+  // request related signals
+  typedef struct packed {
+    logic                           wr;
+    logic                           rd;
+    logic [    CTRLPORT_ADDR_W-1:0] addr;
+    logic [  CTRLPORT_PORTID_W-1:0] port_id;
+    logic [CTRLPORT_REM_EPID_W-1:0] remote_epid;
+    logic [  CTRLPORT_PORTID_W-1:0] remote_portid;
+    logic [    CTRLPORT_DATA_W-1:0] data;
+    logic [ CTRLPORT_BYTE_EN_W-1:0] byte_en;
+    logic                           has_time;
+    // signal time - renamed to timestamp to avoid conflict with SystemVerilog keyword time
+    logic [    CTRLPORT_TIME_W-1:0] timestamp;
+  } ctrlport_request_t;
+
+  // response related signals
+  typedef struct packed {
+    logic                       ack;
+    ctrlport_status_t           status;
+    logic [CTRLPORT_DATA_W-1:0] data;
+  } ctrlport_response_t;
+
 endpackage : ctrlport_pkg