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fpga: tools: Fix HLS IP build with Cygwin

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Original-commit: be252febd001feac093b36c987d276720e4244ab
This commit is contained in:
Humberto Jimenez
2020-05-12 13:47:20 -05:00
committed by Wade Fife
parent 5188f1a6d5
commit f5a79baba7
2 changed files with 10 additions and 4 deletions
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tools/scripts/viv_generate_hls_ip.tcl
+6 -1
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@@ -8,7 +8,12 @@
set part_name $::env(PART_NAME) ;# Full Xilinx part name
set hls_ip_name $::env(HLS_IP_NAME) ;# High level synthesis IP name
set hls_ip_srcs $::env(HLS_IP_SRCS) ;# High level synthesis IP source files
set hls_ip_inc $::env(HLS_IP_INCLUDES) ;# High level synthesis IP include directories
if {[info exists env(HLS_IP_INCLUDES)]} {
set hls_ip_inc $::env(HLS_IP_INCLUDES); # High level synthesis IP include directories
} else {
set hls_ip_inc {}
}
# ---------------------------------------
# Vivado Commands