miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: rfnoc: fft: Use DEFAULT on reset in axis_cp_list

Browse Source 
Original-commit: 2eba2e9303d84e1a66f9841f894d526f62d91901
This commit is contained in:
Wade Fife
2025-02-12 22:06:20 -06:00
parent ac04bb81c4
commit f480008cf9
1 changed files with 12 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/rfnoc/blocks/rfnoc_block_fft/axis_cp_list.sv
+4 -4
View File
@@ -52,11 +52,11 @@ module axis_cp_list #(
input wire i_tvalid, input wire i_tvalid,
output wire i_tready, output wire i_tready,
output reg [DATA_W-1:0] o_tdata, output logic [DATA_W-1:0] o_tdata = DEFAULT,
output reg o_tvalid, output logic o_tvalid,
input wire o_tready, input wire o_tready,
output wire [ADDR_W:0] occupied output wire [ ADDR_W:0] occupied
); );
// Make addresses one extra bit wide to double as fullness and to detect the // Make addresses one extra bit wide to double as fullness and to detect the
@@ -156,7 +156,7 @@ module axis_cp_list #(
if (rst | clear) begin if (rst | clear) begin
rd_state <= ST_IDLE; rd_state <= ST_IDLE;
rd_addr <= '0; rd_addr <= '0;
o_tdata <= '0; o_tdata <= DEFAULT;
o_tvalid <= '0; o_tvalid <= '0;
end end
end end