fpga: lib: Add advanced features to IPv4 SV transport adapter
This adds several features to the SystemVerilog Eth/IPv4/UDP transport adaptor including: - Compat register - NODE_INST register - Capabilities register - KV map access for custom routing on RX data paths - CHDR header removal for raw payloads to be sent over UDP Also adds xport_adapter_ctrl.py, which allows controlling the new registers. Co-authored-by: Martin Braun <martin.braun@ettus.com> Original-commit: 3c3da4c62f33d02bb05bcdc38e8929cbf2cdd9a3
This commit is contained in:
Wade Fife
committed by
skooNI
skooNI
co-authored by
Martin Braun
Martin Braun
parent
cad2f7ba5c
commit
f2b4426b0f
@@ -1,49 +1,75 @@
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//
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// Copyright 2020 Ettus Research, A National Instruments Brand
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: eth_ipv4_chdr_adapter
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// Description: A generic transport adapter module that can be used in
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// a variety of transports. It does the following:
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// - Exposes a configuration port for mgmt packets to configure the node
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// - Implements a return-address map for packets with metadata other than
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// the CHDR. Additional metadata can be passed as a tuser to this module
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// which will store it in a map indexed by the SrcEPID in a management
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// packet. For all returning packets, the metadata will be looked up in
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// the map and attached as the outgoing tuser.
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// - Implements a loopback path for node-info discovery
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//
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// Description:
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//
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// An Eth+IP+UDP transport adapter for RFNoC. In the RFNoC-to-Eth direction,
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// this module encapsulates CHDR packets (or just the CHDR packet's payload)
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// inside UDP/IP/Eth packets to be sent onto the network. In the other
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// direction, this module looks at the UDP port in the packet to determine if
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// it's a CHDR packet destined for RFNoC or a packet destined for the CPU,
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// then routes the packet accordingly. If it's destined for RFNoC, the
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// Eth/UDP/IP headers are stripped off.
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//
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// Traffic to/from the CPU can only go from/to the Eth interface. Traffic
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// to/from RFNoC can only go from/to the Eth interface. There's no path
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// between the CPU and RFNoC.
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//
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// (CPU)
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// e2c c2e
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// ▲ │
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// │ │
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// │ ▼
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// ┌───┼───┼───┐
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// │ │ │ |
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// eth_tx ◄────┼───┼───█───┼◄──── v2e
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// (UDP/IP/Eth) │ │ │ (RFNoC CHDR)
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// eth_rx ────►┼───█───────┼────► e2v
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// | |
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// └───────────┘
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// Transport Adapter
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//
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// Parameters:
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// - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
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// - CPU_FIFO_SIZE: Log2 of the FIFO depth (in bytes) for the CPU egress path
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// - CHDR_FIFO_SIZE: Log2 of the FIFO depth (in bytes) for the CHDR egress path
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// - RT_TBL_SIZE: Log2 of the depth of the return-address routing table
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// - NODE_INST: The node type to return for a node-info discovery
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// - DROP_UNKNOWN_MAC: Drop packets not addressed to us?
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// - DROP_MIN_PACKET: Drop packets smaller than 64 bytes?
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// - PREAMBLE_BYTES: Number of bytes of Preamble expected
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// - ADD_SOF: Add a SOF indication into the tuser field of the e2c path.
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// If false use TKEEP instead of USER.
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// - SYNC: Set if the CPU clock domain (c2e, e2c) is not the same as the
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// Ethernet clock domain (eth_rx, eth_tx).
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// - ENET_W: Width of the link to the Ethernet MAC
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// - CPU_W: Width of the CPU interface
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// - CHDR_W: CHDR width used by RFNoC on the FPGA
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// - NET_CHDR_W: CHDR width used over the network connection
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//
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// PROTOVER : RFNoC protocol version {8'd<major>, 8'd<minor>}
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// CPU_FIFO_SIZE : Log2 of the FIFO depth (in bytes) for the CPU egress path
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// CHDR_FIFO_SIZE : Log2 of the FIFO depth (in bytes) for the CHDR egress path
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// RT_TBL_SIZE : Log2 of the depth of the return-address routing table
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// NODE_INST : The node type to return for a node-info discovery
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// DROP_UNKNOWN_MAC : Drop packets not addressed to us?
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// DROP_MIN_PACKET : Drop packets smaller than 64 bytes?
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// PREAMBLE_BYTES : Number of bytes of Preamble expected
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// ADD_SOF : Add a SOF indication into the tuser field of the e2c
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// path. If false use TKEEP instead of USER.
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// SYNC : Set to 1 if the c2e/e2c, v2e/e2v, and eth_rx/eth_tx are
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// synchronous to each other. Set to 0 to insert clock
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// crossing logic.
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// ENET_W : Width of the link to the Ethernet MAC
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// CPU_W : Width of the CPU interface
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// CHDR_W : CHDR width used by RFNoC on the FPGA
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// NET_CHDR_W : CHDR width used over the network connection
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// EN_RX_RAW_PAYD : Enable CHDR header removal (raw payload) on v2e path
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//
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// Signals:
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// - device_id : The ID of the device that has instantiated this module
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// - eth_rx : The input Ethernet stream from the MAC
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// - eth_tx : The output Ethernet stream to the MAC
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// - v2e : The input CHDR stream from the rfnoc infrastructure
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// - e2v : The output CHDR stream to the rfnoc infrastructure
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// - c2e : The input Ethernet stream from the CPU
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// - e2c : The output Ethernet stream to the CPU
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// - my_mac: The Ethernet (MAC) address of this endpoint
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// - my_ip: The IPv4 address of this endpoint
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// - my_udp_chdr_port: The UDP port allocated for CHDR traffic on this endpoint
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//
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// device_id : The ID of the device that has instantiated this module
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// eth_rx : The input Ethernet stream from the MAC
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// eth_tx : The output Ethernet stream to the MAC
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// v2e : The input CHDR stream from the rfnoc infrastructure
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// e2v : The output CHDR stream to the rfnoc infrastructure
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// c2e : The input Ethernet stream from the CPU
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// e2c : The output Ethernet stream to the CPU
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// my_mac : The Ethernet (MAC) address of this endpoint
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// my_ip : The IPv4 address of this endpoint
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// my_udp_chdr_port : The UDP port allocated for CHDR traffic on this endpoint
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//
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`default_nettype none
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module eth_ipv4_chdr_adapter #(
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logic [15:0] PROTOVER = {8'd1, 8'd0},
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@@ -59,18 +85,30 @@ module eth_ipv4_chdr_adapter #(
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int ENET_W = 64,
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int CPU_W = 64,
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int CHDR_W = 64,
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int NET_CHDR_W = CHDR_W
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int NET_CHDR_W = CHDR_W,
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bit EN_RX_RAW_PYLD = 1
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)(
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// Device info
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input logic [15:0] device_id,
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// Device addresses
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input logic [47:0] my_mac,
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input logic [31:0] my_ip,
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input logic [15:0] my_udp_chdr_port,
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input logic [15:0] my_pause_set,
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input logic [15:0] my_pause_clear,
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input wire [15:0] device_id,
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// Device addresses
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input wire [47:0] my_mac,
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input wire [31:0] my_ip,
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input wire [15:0] my_udp_chdr_port,
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input wire [15:0] my_pause_set,
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input wire [15:0] my_pause_clear,
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// Key-value map interface
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input wire kv_stb,
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output wire kv_busy,
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input wire [47:0] kv_mac_addr,
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input wire [31:0] kv_ip_addr,
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input wire [15:0] kv_udp_port,
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input wire [15:0] kv_dst_epid,
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input wire kv_raw_udp,
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// Dropped packet debug values
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output logic chdr_dropped,
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output logic cpu_dropped,
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@@ -229,23 +267,30 @@ module eth_ipv4_chdr_adapter #(
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v2e3(eth_rx.clk,eth_rx.rst);
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chdr_xport_adapter #(
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.PREAMBLE_BYTES (PREAMBLE_BYTES),
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.MAX_PACKET_BYTES (MAX_PACKET_BYTES),
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.PROTOVER (PROTOVER),
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.TBL_SIZE (RT_TBL_SIZE),
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.NODE_INST (NODE_INST),
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.ALLOW_DISC (1),
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.NET_CHDR_W (NET_CHDR_W)
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) xport_adapter_gen_i (
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.device_id (device_id),
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.my_mac (my_mac),
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.my_ip (my_ip),
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.my_udp_chdr_port (my_udp_chdr_port),
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.eth_rx (e2v2), // from Ethernet
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.e2v (e2v3), // to CHDR
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// Optional loop from Ethernet to Ethernet to talk to node
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.v2e (v2e), // from CHDR
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.eth_tx (v2e1D) // to Ethernet
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.PREAMBLE_BYTES (PREAMBLE_BYTES ),
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.MAX_PACKET_BYTES(MAX_PACKET_BYTES),
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.PROTOVER (PROTOVER ),
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.TBL_SIZE (RT_TBL_SIZE ),
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.NODE_INST (NODE_INST ),
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.ALLOW_DISC (1 ),
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.NET_CHDR_W (NET_CHDR_W ),
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.EN_RX_RAW_PYLD (EN_RX_RAW_PYLD )
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) chdr_xport_adapter_i (
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.device_id (device_id ),
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.my_mac (my_mac ),
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.my_ip (my_ip ),
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.my_udp_chdr_port(my_udp_chdr_port),
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.kv_stb (kv_stb ),
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.kv_busy (kv_busy ),
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.kv_dst_epid (kv_dst_epid ),
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.kv_data ({kv_raw_udp,
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kv_udp_port,
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kv_ip_addr,
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kv_mac_addr }),
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.eth_rx (e2v2 ), // from Ethernet
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.e2v (e2v3 ), // to CHDR
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.v2e (v2e ), // from CHDR
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.eth_tx (v2e1D ) // to Ethernet
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);
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if (DEBUG) begin
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@@ -494,4 +539,7 @@ module eth_ipv4_chdr_adapter #(
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);
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endmodule // eth_ipv4_chdr_adapter
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endmodule : eth_ipv4_chdr_adapter
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`default_nettype wire
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