fpga: e31x: Change image file to e310_rfnoc_image_core

This renames e31x_rfnoc_image_core.* to e310_rfnoc_image_core.*. This
makes the naming consistent with the rest of the build process (which
uses "e310" for all variants of e31x) and fixes an issue in which the
wrong file name was used by rfnoc_image_builder.


Original-commit: bbd43b16e18ef0a0311ddf4635cbd29c4ac3c367

top/e31x/Makefile

@@ -26,7 +26,7 @@ ifndef TARGET
 endif
 TOP ?= e31x
 
-DEFAULT_IMAGE_CORE_FILE_E31X=e31x_rfnoc_image_core.v
+DEFAULT_IMAGE_CORE_FILE_E31X=e310_rfnoc_image_core.v
 DEFAULT_EDGE_FILE_E31X=$(abspath e310_static_router.hex)
 
 # vivado_build($1=Device, $2=Definitions)

top/e31x/e310_rfnoc_image_core.v

@@ -1,5 +1,5 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2020 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -7,9 +7,9 @@
 // Module: rfnoc_image_core (for e31x)
 // This file was autogenerated by UHD's image builder tool (rfnoc_image_builder)
 // Re-running that tool will overwrite this file!
-// File generated on: 2019-11-08T15:58:15.219909
-// Source: ./e31x/e31x_rfnoc_image_core.yml
-// Source SHA256: 48e2907163bf8462812f33b7cf995da37c44d9652ba3afa38c510910a2365c05
+// File generated on: 2020-09-08T10:54:16.062742
+// Source: e310_rfnoc_image_core.yml
+// Source SHA256: 00908abb846aaf175d1f8f2e75c6d39a3cd4958b326ab3125f4a1023c7b78b39
 
 module rfnoc_image_core #(
   parameter [15:0] PROTOVER = {8'd1, 8'd0}