From f19fa3cf827cb00a1fff3f4e9e7320a9675ff6eb Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Sat, 8 Feb 2025 17:18:35 -0600 Subject: [PATCH] fpga: rfnoc: Fix info FIFO overflow In cases when the info FIFO fills, it was possible for in_pkt_info_tvalid to be asserted then on the next cycle in_pkt_info_tready would deassert, in which case the input would be dropped. This change ensures that tvalid remains asserted until tready deasserts. Original-commit: 6d2e9f983ae94d2e1e6866c34b3c87374a349631 --- lib/rfnoc/core/axis_data_to_chdr.v | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/rfnoc/core/axis_data_to_chdr.v b/lib/rfnoc/core/axis_data_to_chdr.v index d6b0a4d..a6c61b5 100644 --- a/lib/rfnoc/core/axis_data_to_chdr.v +++ b/lib/rfnoc/core/axis_data_to_chdr.v @@ -178,10 +178,11 @@ module axis_data_to_chdr #( if (axis_data_rst) begin in_pkt_info_tvalid <= 1'b0; end else begin - in_pkt_info_tvalid <= 1'b0; if (s_axis_tvalid && s_axis_tready && start_of_packet) begin packet_length <= s_axis_tlength + HDR_LEN; in_pkt_info_tvalid <= 1'b1; + end else if (in_pkt_info_tready) begin + in_pkt_info_tvalid <= 1'b0; end end end @@ -207,7 +208,9 @@ module axis_data_to_chdr #( end // Update the packet length if the word is accepted - in_pkt_info_tvalid <= 1'b0; + if (in_pkt_info_tready) begin + in_pkt_info_tvalid <= 1'b0; + end if (s_axis_tvalid && s_axis_tready) begin if (s_axis_tlast) begin length_count <= HDR_LEN;