fpga: Put dependencies first in Makefile SRCS list

Original-commit: 0de3eb63bba518d94058c985d759958caac388d5
2024-09-06 17:58:33 -05:00
parent 71c7b9044d
commit f13f084b15
5 changed files with 38 additions and 38 deletions
@@ -68,10 +68,7 @@ endif
 DRAM_SRCS = $(IP_DRAM_XCI_SRCS)
-# The XDC files must be read in a specific order, motherboard first and then daughterboard.
+DESIGN_SRCS = $(abspath \
 # Outside of that, all the other sources can be read in any order desired.
 DESIGN_SRCS = \
 $(abspath $(TOP_SRCS)) \
 $(CONTROL_LIB_SRCS) \
 $(IP_XCI_SRCS) \
 $(XGE_INTERFACE_SRCS) \
@@ -91,12 +88,13 @@ $(LIB_IP_XCI_SRCS) \
 $(LIB_HLS_IP_SRCS) \
 $(EXTRAM_SRCS) \
 $(CAP_GEN_GENERIC_SRCS) \
 $(RFNOC_FRAMEWORK_SRCS) \
 $(RFNOC_SRCS) \
 $(RFNOC_OOT_SRCS)\
 $(RFNOC_FRAMEWORK_SRCS) \
 $(RFNOC_BLOCK_EXAMPLE_SRCS) \
 $(RFNOC_IMAGE_CORE_SRCS) \
-$(abspath $(MB_XDC))
+$(TOP_SRCS) \
 $(MB_XDC) \
 )
 # Pass the image core header files required by RFNoC
 # to Vivado as Verilog definitions.
@@ -83,10 +83,7 @@ else
 DRAM_SRCS =
 endif
-# The XDC files must be read in a specific order, motherboard first and then daughterboard.
+DESIGN_SRCS = $(abspath \
 # Outside of that, all the other sources can be read in any order desired.
 DESIGN_SRCS = \
 $(abspath $(TOP_SRCS)) \
 $(CONTROL_LIB_SRCS) \
 $(IP_XCI_SRCS) \
 $(TEN_GIGE_PHY_SRCS) \
@@ -94,6 +91,7 @@ $(XGE_SRCS) \
 $(XGE_INTERFACE_SRCS) \
 $(PACKET_PROC_SRCS) \
 $(AXI_SRCS) \
 $(AXI4S_SV_SRCS) \
 $(FIFO_SRCS) \
 $(ONE_GIGE_PHY_SRCS) \
 $(SIMPLE_GEMAC_SRCS) \
@@ -108,12 +106,14 @@ $(LIB_IP_XCI_SRCS) \
 $(LIB_HLS_IP_SRCS) \
 $(EXTRAM_SRCS) \
 $(CAP_GEN_GENERIC_SRCS) \
 $(RFNOC_FRAMEWORK_SRCS) \
 $(RFNOC_SRCS) \
 $(RFNOC_OOT_SRCS) \
-$(RFNOC_FRAMEWORK_SRCS) \
+$(RFNOC_XPORT_SV_SRCS) \
-$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
+$(RFNOC_IMAGE_CORE_SRCS) \
-$(abspath $(MB_XDC)) \
+$(TOP_SRCS) \
-$(RFNOC_IMAGE_CORE_SRCS)
+$(MB_XDC) \
 )
 IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
@@ -117,11 +117,10 @@ endif
 DB_SRCS += $(DB_COMMON_SRCS)
-# The XDC files must be read in a specific order, motherboard first and then daughterboard,
+# The XDC files must be read in a specific order, motherboard first and then
-# and the clocking XDC files must be before other XDC files.
+# daughterboard, and the clocking XDC files must be before other XDC files.
-# Outside of that, all the other sources can be read in any order desired.
+DESIGN_SRCS = $(abspath \
-DESIGN_SRCS = $(MB_CLOCKS_XDC) $(DB_CLOCKS_XDC) $(abspath $(MB_XDC)) $(DB_SRCS) \
+$(AXI_SRCS) $(AXI4S_SV_SRCS) $(FIFO_SRCS) \
 $(abspath $(TOP_SRCS)) $(AXI_SRCS) $(FIFO_SRCS) \
 $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
 $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
 $(UDP_SRCS) $(EXTRAM_SRCS) $(WISHBONE_SRCS) \
@@ -129,11 +128,13 @@ $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(AURORA_PHY_SRCS) \
 $(TEN_GIGE_PHY_SRCS) $(ONE_GIGE_PHY_SRCS) \
 $(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
 $(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
 $(RFNOC_FRAMEWORK_SRCS) \
 $(RFNOC_SRCS) $(RFNOC_OOT_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) \
 $(WHITE_RABBIT_SRCS) \
-$(RFNOC_FRAMEWORK_SRCS) \
+$(RFNOC_XPORT_SV_SRCS) \
 $(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
 $(RFNOC_IMAGE_CORE_SRCS) \
 $(MB_CLOCKS_XDC) $(DB_CLOCKS_XDC) $(MB_XDC) $(DB_SRCS) $(TOP_SRCS) \
 )
 # Pass the image core header files required by RFNoC
 # to Vivado as Verilog definitions.
@@ -93,19 +93,22 @@ else
 DRAM_SRCS =
 endif
-DESIGN_SRCS = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+# The XDC files must be read in a specific order, motherboard (TOP_SRCS) first
 # and then SFP (SFP_SERDES_SRCS) and DRAM (DRAM_SRCS).
 DESIGN_SRCS = $(abspath $(FIFO_SRCS) \
 $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
 $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
 $(UDP_SRCS) $(EXTRAM_SRCS) \
 $(ZPU_CORE_SRCS) $(WISHBONE_SRCS) \
-$(SFP_SERDES_SRCS) $(IOPORT2_SRCS) \
+$(IOPORT2_SRCS) \
-$(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
+$(PACKET_PROC_SRCS) $(DSP_SRCS) \
-$(AXI_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
+$(AXI_SRCS) $(AXI4S_SV_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
-$(RFNOC_SRCS) $(LIB_IP_XCI_SRCS) \
+$(LIB_IP_XCI_SRCS) \
-$(RFNOC_FRAMEWORK_SRCS) \
+$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_SRCS) $(RFNOC_OOT_SRCS) \
-$(RFNOC_OOT_SRCS) \
+$(RFNOC_XPORT_SV_SRCS) \
-$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
+$(RFNOC_IMAGE_CORE_SRCS) \
-$(RFNOC_IMAGE_CORE_SRCS)
+$(TOP_SRCS) $(SFP_SERDES_SRCS) $(DRAM_SRCS) \
 )
 # Pass the image core header files required by RFNoC
 # to Vivado as Verilog definitions.
@@ -143,10 +143,8 @@ MB_XDC += $(RFNOC_XDC_SRCS)
 DESIGN_SRCS = $(abspath $(MB_XDC))
 # The XDC files must be read in a specific order, motherboard first and then daughterboard.
 # Outside of that, all the other sources can be read in any order desired.
 DESIGN_SRCS += $(abspath \
-$(AXI4_SV_SRCS) $(AXI4S_SV_SRCS) $(AXI4LITE_SV_SRCS) $(TOP_SRCS) \
+$(AXI4_SV_SRCS) $(AXI4S_SV_SRCS) $(AXI4LITE_SV_SRCS) \
 $(AXI_SRCS) $(FIFO_SRCS) \
 $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
 $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
@@ -155,10 +153,10 @@ $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(AURORA_PHY_SRCS) \
 $(XGE_PCS_PMA_SRCS) \
 $(PACKET_PROC_SRCS) $(VITA_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
 $(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
-$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) $(LIBCOREGEN_SRCS) \
+$(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) $(LIBCOREGEN_SRCS) $(WB_SPI_SRCS) \
-$(DB_COMMON_SRCS) $(RFNOC_FRAMEWORK_SRCS) \
+$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_SRCS) $(RFNOC_OOT_SRCS) \
-$(WB_SPI_SRCS) $(RFNOC_XPORT_SV_SRCS) \
+$(RFNOC_XPORT_SV_SRCS) $(RFNOC_IMAGE_CORE_SRCS) \
-$(RFNOC_IMAGE_CORE_SRCS) \
+$(DB_COMMON_SRCS) $(TOP_SRCS) \
 )
 # Pass the image core header files required by RFNoC