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fpga: Put dependencies first in Makefile SRCS list

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Original-commit: 0de3eb63bba518d94058c985d759958caac388d5
This commit is contained in:
Wade Fife
2024-09-06 17:58:33 -05:00
parent 71c7b9044d
commit f13f084b15
5 changed files with 38 additions and 38 deletions
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top/x300/Makefile.x300.inc
+12 -9
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@@ -93,19 +93,22 @@ else
DRAM_SRCS =
endif
DESIGN_SRCS = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
# The XDC files must be read in a specific order, motherboard (TOP_SRCS) first
# and then SFP (SFP_SERDES_SRCS) and DRAM (DRAM_SRCS).
DESIGN_SRCS = $(abspath $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
$(UDP_SRCS) $(EXTRAM_SRCS) \
$(ZPU_CORE_SRCS) $(WISHBONE_SRCS) \
$(SFP_SERDES_SRCS) $(IOPORT2_SRCS) \
$(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
$(AXI_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
$(RFNOC_SRCS) $(LIB_IP_XCI_SRCS) \
$(RFNOC_FRAMEWORK_SRCS) \
$(RFNOC_OOT_SRCS) \
$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
$(RFNOC_IMAGE_CORE_SRCS)
$(IOPORT2_SRCS) \
$(PACKET_PROC_SRCS) $(DSP_SRCS) \
$(AXI_SRCS) $(AXI4S_SV_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
$(LIB_IP_XCI_SRCS) \
$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_SRCS) $(RFNOC_OOT_SRCS) \
$(RFNOC_XPORT_SV_SRCS) \
$(RFNOC_IMAGE_CORE_SRCS) \
$(TOP_SRCS) $(SFP_SERDES_SRCS) $(DRAM_SRCS) \
)
# Pass the image core header files required by RFNoC
# to Vivado as Verilog definitions.