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fpga: Fix target dependencies in Makefile.xxx.inc

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Original-commit: e0147fd19347e4e2b2ec1cae193d4c295b9c427b
This commit is contained in:
Wade Fife
2022-08-29 07:53:32 -05:00
parent ea58284d4d
commit f010ce051e
5 changed files with 21 additions and 21 deletions
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top/n3xx/Makefile.n3xx.inc
+5 -5
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@@ -152,16 +152,16 @@ IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs $$(DESIGN_SRCS)
bin: .prereqs
$(call BUILD_VIVADO_DESIGN,$(abspath ./build_n3xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
synth: .prereqs $$(DESIGN_SRCS)
synth: .prereqs
$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
rtl: .prereqs $$(DESIGN_SRCS)
rtl: .prereqs
$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
viv_ip: .prereqs $$(DESIGN_SRCS)
viv_ip: .prereqs $$(DESIGN_SRCS) ip
@echo "IP build for $(NAME) DONE . . ."
.PHONY: bin rtl
.PHONY: bin synth rtl viv_ip