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fpga: Add BUILD_BASE_DIR option to makefiles

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Adds a BUILD_BASE_DIR makefile variable that allows you to specify the
base directory for FPGA build outputs. This allows you to put the
output from each run of make into a unique directory, or to run
multiple instances of make in parallel with each build's output being
put in a different directory. For example:

make X310_XG BUILD_BASE_DIR=/path/to/builds


Original-commit: bc6db8409ba756bbad0d0c158ffb00c614b58fd9
This commit is contained in:
Wade Fife
2023-02-09 07:38:49 -06:00
parent c525cba09c
commit eec959f814
8 changed files with 35 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files
tools/make/diamond_preamble.mak
+3 -3
View File
@@ -23,12 +23,12 @@ endif
TOOLS_DIR = $(BASE_DIR)/../tools
LIB_DIR = $(BASE_DIR)/../lib
O ?= .
BUILD_BASE_DIR ?= .
ifdef NAME
BUILD_DIR = $(abspath $(O)/build-$(NAME))
BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build-$(NAME))
else
BUILD_DIR = $(abspath $(O)/build)
BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build)
endif
IP_BUILD_DIR = $(abspath ./build-ip/$(subst /,,$(PART_ID)))
tools/make/quartus_preamble.mak
+3 -3
View File
@@ -23,12 +23,12 @@ endif
TOOLS_DIR = $(BASE_DIR)/../tools
LIB_DIR = $(BASE_DIR)/../lib
O ?= .
BUILD_BASE_DIR ?= .
ifdef NAME
BUILD_DIR = $(abspath $(O)/build-$(NAME))
BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build-$(NAME))
else
BUILD_DIR = $(abspath $(O)/build)
BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build)
endif
IP_BUILD_DIR = $(abspath ./build-ip/$(subst /,,$(PART_ID)))
tools/make/viv_preamble.mak
+3 -3
View File
@@ -24,12 +24,12 @@ SIMLIB_DIR = $(abspath $(BASE_DIR)/../sim)
LIB_IP_DIR = $(abspath $(LIB_DIR)/ip)
HLS_IP_DIR = $(abspath $(LIB_DIR)/hls)
O ?= .
BUILD_BASE_DIR ?= .
ifdef NAME
BUILD_DIR = $(abspath $(O)/build-$(NAME))
BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build-$(NAME))
else
BUILD_DIR = $(abspath $(O)/build)
BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build)
endif
IP_BUILD_DIR = $(abspath ./build-ip/$(subst /,,$(PART_ID)))
top/e31x/Makefile
+5 -2
View File
@@ -14,6 +14,9 @@
## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file
## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
# Base output directory for all builds
BUILD_BASE_DIR ?= .
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
DEFS += BUILD_SEED=$(BUILD_SEED)
@@ -42,9 +45,9 @@ ifeq ($(TARGET),bin)
post_build = @\
mkdir -p build; \
echo "Exporting bitstream file..."; \
cp build-$(1)/e31x.bit build/usrp_`echo $(2) | tr A-Z a-z`_fpga.bit; \
cp $(BUILD_BASE_DIR)/build-$(1)/e31x.bit build/usrp_`echo $(2) | tr A-Z a-z`_fpga.bit; \
echo "Exporting build report..."; \
cp build-$(1)/build.rpt build/usrp_`echo $(2) | tr A-Z a-z`_fpga.rpt; \
cp $(BUILD_BASE_DIR)/build-$(1)/build.rpt build/usrp_`echo $(2) | tr A-Z a-z`_fpga.rpt; \
echo "Build DONE ... $(1)";
else
post_build = @echo "Skipping bitfile export."
top/e320/Makefile
+5 -2
View File
@@ -14,6 +14,9 @@
## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file
## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
# Base output directory for all builds
BUILD_BASE_DIR ?= .
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
@@ -45,9 +48,9 @@ ifeq ($(TARGET),bin)
post_build = @\
mkdir -p build; \
echo "Exporting bitstream file..."; \
cp build-$(1)_$(2)/e320.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/e320.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
echo "Exporting build report..."; \
cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
echo "Build DONE ... $(1)_$(2)";
else
post_build = @echo "Skipping bitfile export."
top/n3xx/Makefile
+5 -2
View File
@@ -23,6 +23,9 @@
# Uncomment this line to add four example Aurora loopback lanes on the QSFP NPIO bus.
# OPTIONS += QSFP_LANES=4
# Base output directory for all builds
BUILD_BASE_DIR ?= .
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
@@ -68,9 +71,9 @@ ifeq ($(TARGET),bin)
post_build = @\
mkdir -p build; \
echo "Exporting bitstream file..."; \
cp build-$(1)_$(2)/n3xx.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/n3xx.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
echo "Exporting build report..."; \
cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
echo "Build DONE ... $(1)_$(2)";
else
post_build = @echo "Skipping bitfile export."
top/x300/Makefile
+7 -4
View File
@@ -21,6 +21,9 @@
CREATE_LVBITX=python ../../lib/io_port2/create-lvbitx.py
# Base output directory for all builds
BUILD_BASE_DIR ?= .
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
@@ -56,13 +59,13 @@ ifeq ($(TARGET),bin)
post_build = @\
mkdir -p build; \
echo "Exporting bitstream files..."; \
cp build-$(1)_$(2)/x300.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
cp build-$(1)_$(2)/x300.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
echo "Generating LVBITX..."; \
$(CREATE_LVBITX) --input-bin=build-$(1)_$(2)/x300.bin --output-lvbitx=build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
$(CREATE_LVBITX) --input-bin=$(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bin --output-lvbitx=build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
cp -f x3x0_base.lvbitx build/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
echo "Exporting build report..."; \
cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
echo "Build DONE ... $(1)_$(2)";
else
post_build = @echo "Skipping bitfile export."
top/x400/Makefile
+4 -3
View File
@@ -16,7 +16,8 @@
## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file
## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
# Base output directory for all builds
BUILD_BASE_DIR ?= .
# Definitions
# MGT Types from x4xx_mgt_type.vh
@@ -97,9 +98,9 @@ ifeq ($(TARGET),bin)
post_build = @\
mkdir -p build; \
echo "Exporting bitstream file..."; \
cp build-$(1)_$(2)/x4xx.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x4xx.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
echo "Exporting build report..."; \
cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
echo "Build DONE ... $(1)_$(2)";
else
post_build = @echo "Skipping bitfile export."