fpga: Remove Python2 support from build system
- 2to3 was used to convert the Python scripts, except where the tool choked and manual intervention was required - All references to "python" where replaced with "python3" - buffer() was replaced by memoryview() Original-commit: ca68195b5d12c5410cfac8d459a0b0902c4c72c7
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@@ -1,4 +1,4 @@
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#!/usr/bin/env python
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#!/usr/bin/env python3
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#
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# Notice: Some parts of this file were copied from PyBOMBS, which has a
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# different copyright, and is highlighted appropriately. The following
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@@ -24,7 +24,6 @@
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Run Vivado builds
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"""
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from __future__ import print_function
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import os
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import sys
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import re
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@@ -34,10 +33,7 @@ import time
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import argparse
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import subprocess
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import threading
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try:
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from Queue import Queue, Empty
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except ImportError:
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from queue import Queue, Empty # Py3k
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from queue import Queue, Empty
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READ_TIMEOUT = 0.1 # s
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@@ -472,4 +468,3 @@ def main():
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if __name__ == "__main__":
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exit(not main())
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@@ -338,7 +338,7 @@ function viv_create_ip {
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$VIVADO_EXEC -mode gui -source $(resolve_viv_path $VIV_IP_UTILS) -nolog -nojournal -tclargs create $part_name $ip_name $(resolve_viv_path $ip_dir) $ip_vlnv
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echo "Generating Makefile..."
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python $REPO_BASE_PATH/tools/scripts/viv_gen_ip_makefile.py --ip_name=$ip_name --dest=$ip_dir/$ip_name
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python3 $REPO_BASE_PATH/tools/scripts/viv_gen_ip_makefile.py --ip_name=$ip_name --dest=$ip_dir/$ip_name
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echo "Done generating IP in $ip_dir/$ip_name"
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}
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@@ -352,7 +352,7 @@ function viv_modify_ip {
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fi
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xci_path=$(readlink -f $1)
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part_name=$(python $REPO_BASE_PATH/tools/scripts/viv_ip_xci_editor.py read_part $xci_path)
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part_name=$(python3 $REPO_BASE_PATH/tools/scripts/viv_ip_xci_editor.py read_part $xci_path)
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if [[ -z $part_name ]]; then
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echo "ERROR: Invalid part name $part_name. XCI parse error."
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return 1
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@@ -446,7 +446,7 @@ function viv_upgrade_ip {
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for xci_path in $xci_files; do
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if [[ -f $xci_path ]]; then
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echo "Upgrading $xci_path..."
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part_name=$(python $REPO_BASE_PATH/tools/scripts/viv_ip_xci_editor.py read_part $xci_path)
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part_name=$(python3 $REPO_BASE_PATH/tools/scripts/viv_ip_xci_editor.py read_part $xci_path)
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$VIVADO_EXEC -mode batch -source $(resolve_viv_path $VIV_IP_UTILS) -nolog -nojournal -tclargs upgrade $part_name $(resolve_viv_path $xci_path) | grep -v -E '(^$|^#|\*\*)'
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test ${PIPESTATUS[0]} -eq 0
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else
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@@ -494,7 +494,7 @@ function probe_bitfile {
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echo "- <Bitfile Path>: Path to a .bit FPGA configuration file"
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return 1
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fi
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python $REPO_BASE_PATH/tools/scripts/xil_bitfile_parser.py --info $1
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python3 $REPO_BASE_PATH/tools/scripts/xil_bitfile_parser.py --info $1
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}
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echo
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@@ -1,7 +1,7 @@
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#! /usr/bin/python
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#! /usr/bin/env python3
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import sys, os
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import collections
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import sys
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import os
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import argparse
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import datetime
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@@ -10,7 +10,8 @@ def get_options():
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parser = argparse.ArgumentParser(description='Create a Makefile for Xilinx IP.')
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parser.add_argument('--ip_name', type=str, default=None, help='Name for the IP core')
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parser.add_argument('--dest', type=str, default=None, help='Destination directory')
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parser.add_argument('--copright_auth', type=str, default='Ettus Research', help='Copyright author')
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parser.add_argument('--copright_auth',
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type=str, default='Ettus Research', help='Copyright author')
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args = parser.parse_args()
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if not args.ip_name:
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print('ERROR: Please specify a name for the IP core\n')
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@@ -39,13 +40,13 @@ $({ip_srcs_var}) $({ip_outs_var}) : $(IP_DIR)/{ip_name}/{ip_name}.xci
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"""
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def main():
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args = get_options();
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args = get_options()
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transform = {}
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transform['ip_name'] = args.ip_name
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transform['ip_srcs_var'] = 'IP_' + args.ip_name.upper() + '_SRCS'
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transform['ip_outs_var'] = 'IP_' + args.ip_name.upper() + '_OUTS'
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transform['copyright'] = 'Copyright ' + str(datetime.datetime.now().year) + ' ' + args.copright_auth
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transform['copyright'] = 'Copyright {} {}'.format(
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datetime.datetime.now().year, args.copright_auth)
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with open(os.path.join(args.dest, 'Makefile.inc'), 'w') as mak_file:
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mak_file.write(g_makefile_template.format(**transform))
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@@ -1,8 +1,7 @@
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#!/usr/bin/python
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#!/usr/bin/env python3
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import argparse
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import os, sys
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import re
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import sys
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# Parse command line options
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def get_options():
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@@ -21,7 +20,7 @@ def main():
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target_tok = args.target.split('/')
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if len(target_tok) < 4:
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print('ERROR: Invalid target format. Must be <arch>/<device>/<package>/<speedgrade>[/<temperaturegrade>[/<silicon_revision>]]')
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print('ERROR: Parsed only ' + str(len(target_tok)) + ' tokens')
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print('ERROR: Parsed only ' + str(len(target_tok)) + ' tokens')
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sys.exit(1)
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if target_tok[0] in ['artix7', 'kintex7', 'zynq', 'spartan7', 'virtex7']:
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print('' + target_tok[1] + target_tok[2] + target_tok[3])
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@@ -1,7 +1,8 @@
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#!/usr/bin/python
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#!/usr/bin/env python3
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import argparse
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import os, sys
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import os
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import sys
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import re
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# Parse command line options
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@@ -20,7 +21,7 @@ def get_options():
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print('ERROR: Please specify the location for the XCI file to operate on\n')
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parser.print_help()
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sys.exit(1)
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if (not os.path.isfile(args.xci_filepath)):
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if not os.path.isfile(args.xci_filepath):
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print('ERROR: XCI File ' + args.xci_filepath + ' could not be accessed or is not a file.\n')
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parser.print_help()
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sys.exit(1)
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@@ -59,7 +60,7 @@ def main():
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print(xci_info['DEVICE'] + xci_info['PACKAGE'] + xci_info['SPEEDGRADE'])
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elif args.action == 'retarget':
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# Write a new XCI file with modified target info
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if (not os.path.isdir(args.output_dir)):
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if not os.path.isdir(args.output_dir):
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print('ERROR: IP Build directory ' + args.output_dir + ' could not be accessed or is not a directory.')
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sys.exit(1)
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if not args.target:
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@@ -76,16 +77,16 @@ def main():
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replace_dict['TEMPERATURE_GRADE'] = target_tok[4]
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if len(target_tok) > 5:
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replace_dict['SILICON_REVISION'] = target_tok[5]
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out_xci_filename = os.path.join(os.path.abspath(args.output_dir), os.path.basename(args.xci_filepath))
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out_xci_filename = os.path.join(os.path.abspath(args.output_dir), os.path.basename(args.xci_filepath))
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with open(out_xci_filename, 'w') as out_file:
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for r_line in xci_lines:
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w_line = r_line
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m = re.search(get_match_str('(' + '|'.join(replace_dict.keys()) + ')'), r_line)
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m = re.search(get_match_str('(' + '|'.join(list(replace_dict.keys())) + ')'), r_line)
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if m is not None:
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w_line = m.group(1) + replace_dict[m.group(2)] + m.group(4) +'\n'
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else:
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m = re.search(get_empty_match_str('(' + '|'.join(replace_dict.keys()) + ')'), r_line)
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m = re.search(get_empty_match_str('(' + '|'.join(list(replace_dict.keys())) + ')'), r_line)
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if m is not None:
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w_line = m.group(1) + '>' + replace_dict[m.group(2)] + '</spirit:configurableElementValue>\n'
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out_file.write(w_line)
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@@ -1,7 +1,8 @@
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#!/usr/bin/python
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#!/usr/bin/env python3
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import argparse
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import os, sys
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import os
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import sys
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import struct
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import re
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@@ -13,7 +14,7 @@ def get_options():
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parser.add_argument('--flip', action='store_true', default=False, help='Flip 32-bit endianess')
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parser.add_argument('--info', action='store_true', default=False, help='Print bitfile info')
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args = parser.parse_args()
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if (not os.path.isfile(args.bitfile)):
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if not os.path.isfile(args.bitfile):
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print('ERROR: Bitfile ' + args.bitfile + ' could not be accessed or is not a file.\n')
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parser.print_help()
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sys.exit(1)
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@@ -52,9 +53,9 @@ def parse_bitfile(bitfile_bytes):
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def flip32(data):
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sl = struct.Struct('<I')
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sb = struct.Struct('>I')
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b = buffer(data)
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b = memoryview(data)
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d = bytearray(len(data))
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for offset in xrange(0, len(data), 4):
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for offset in range(0, len(data), 4):
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sb.pack_into(d, offset, sl.unpack_from(b, offset)[0])
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return d
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@@ -67,18 +68,18 @@ def main():
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if args.info:
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m = re.search('(.+);UserID=(.+);COMPRESS=(.+);Version=(.+)', header['design_name'])
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if m:
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print 'Design Name: ' + m.group(1)
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print 'User ID: ' + m.group(2)
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print 'Compression: ' + m.group(3)
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print 'Vivado Version: ' + m.group(4)
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print('Design Name: ' + m.group(1))
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print('User ID: ' + m.group(2))
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print('Compression: ' + m.group(3))
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print('Vivado Version: ' + m.group(4))
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else:
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print 'Design Name: ' + header['design_name']
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print 'Part Name: ' + header['part_name']
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print 'Datestamp: ' + header['date'] + ' ' + header['time']
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print 'Bitstream Size: ' + str(header['bitstream_len'])
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print('Design Name: ' + header['design_name'])
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print('Part Name: ' + header['part_name'])
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print('Datestamp: ' + header['date'] + ' ' + header['time'])
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print('Bitstream Size: ' + str(header['bitstream_len']))
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# Write a bin file
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if args.bin_out:
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open(args.bin_out, 'wb').write(flip32(data) if args.flip else data)
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if __name__ == '__main__':
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main()
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main()
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