diff --git a/top/n3xx/n3xx_clocking.v b/top/n3xx/n3xx_clocking.v
index a1d0770..0eeebb1 100644
--- a/top/n3xx/n3xx_clocking.v
+++ b/top/n3xx/n3xx_clocking.v
@@ -237,11 +237,17 @@ module n3xx_clocking (
   //  ____________|              PPS              |
   // |   Clocks   | External | FPGA  | GPSDO | WR |
   // |--------------------------------------------|
-  // |External 10 |    x     |  x    |       |    |
+  // |External 10 |    x     |  x    |  (x)  |    |
   // |Internal 25 |          |  x    |       | x  |
   // |GPSDO    20 |          |       |   x   |    |
   // |--------------------------------------------|
   //
+  // A note on external clock + GPSDO timing: The hardware doesn't prohibit this
+  // use case, but GPSDO and external clock are guaranteed to be not matched, so
+  // this will certainly cause a non-deterministic time alignment between devices.
+  // Using this combination will still allow receiving samples, but there is no
+  // guarantee regarding phase/time alignment whatsoever.
+  //
   ///////////////////////////////////////////////////////////////////////////////////////
 
   wire pps_ext_refclk;