FPGA: Synchronize X300 RX frontends on time change

The frontend synchronization upon time change was removed, but is
required to synchronize the RX frontend modules when sharing LOs on
TwinRX.  This change restores the behavior.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: c70b479007ab9f578577dfb5c2de6660e877d9a3

top/e31x/e31x_core.v

@@ -683,7 +683,8 @@ module e31x_core #(
    .pps                   (pps_radioclk),
    .tb_timestamp          (radio_time),
    .tb_timestamp_last_pps (),
-   .tb_period_ns_q32      ()
+   .tb_period_ns_q32      (),
+   .tb_changed            ()
   );
 
   /////////////////////////////////////////////////////////////////////////////

top/e320/e320_core.v

@@ -1021,7 +1021,8 @@ module e320_core #(
    .pps                   (pps_radioclk),
    .tb_timestamp          (radio_time),
    .tb_timestamp_last_pps (),
-   .tb_period_ns_q32      ()
+   .tb_period_ns_q32      (),
+   .tb_changed            ()
   );
 
 

top/n3xx/n3xx_core.v

@@ -1109,7 +1109,8 @@ module n3xx_core #(
    .pps                   (pps),
    .tb_timestamp          (radio_time),
    .tb_timestamp_last_pps (),
-   .tb_period_ns_q32      ()
+   .tb_period_ns_q32      (),
+   .tb_changed            ()
   );
 
 

top/x300/bus_int.v

@@ -22,6 +22,7 @@ module bus_int #(
     output [3:0] sw_rst,
     // Timekeeper
     input                   pps,
+    output                  time_sync,
     // Block connections
     input                   ce_clk,
     input                   ce_rst,
@@ -545,7 +546,8 @@ module bus_int #(
      .pps                   (pps),
      .tb_timestamp          (radio_time_tb),
      .tb_timestamp_last_pps (radio_time_last_pps_tb),
-     .tb_period_ns_q32      (period_ns_q32_tb)
+     .tb_period_ns_q32      (period_ns_q32_tb),
+     .tb_changed            (time_sync)
    );
 
    // Latch state changes to SFP0+ pins.

top/x300/x300_core.v

@@ -250,6 +250,7 @@ module x300_core #(
    wire [63:0] s00_axi_rdata, s01_axi_rdata;
    wire [1:0]  s00_axi_rresp, s01_axi_rresp;
    wire [0:0]  s00_axi_ruser, s01_axi_ruser;
+   wire        time_sync;
 
 
    /////////////////////////////////////////////////////////////////////////////////
@@ -287,6 +288,7 @@ module x300_core #(
       .leds(led_misc), .sw_rst(sw_rst),
       // Timekeeper
       .pps(pps_rclk),
+      .time_sync(time_sync),
       // Block connections
       .ce_clk     (ce_clk),
       .ce_rst     (ce_rst),
@@ -609,7 +611,7 @@ module x300_core #(
        ) x300_fe_core_i (
          .clk(radio_clk), .reset(radio_rst),
          .set_stb(db_fe_set_stb[i]), .set_addr(db_fe_set_addr[i]), .set_data(db_fe_set_data[i]),
-         .time_sync(),
+         .time_sync(time_sync),
          .tx_stb(tx_stb_r[i]), .tx_data_in(tx_data_r[i]), .tx_data_out(tx_data_out_r[i]),
          .rx_stb(rx_stb_r[i]), .rx_data_in(rx_data_in_r[i]), .rx_data_out(rx_data_r[i])
        );

top/x400/x4xx_core_common.v

@@ -339,7 +339,8 @@ module x4xx_core_common #(
     .pps                   (pps_radioclk),
     .tb_timestamp          (radio_time),
     .tb_timestamp_last_pps (),
-    .tb_period_ns_q32      ()
+    .tb_period_ns_q32      (),
+    .tb_changed            ()
   );