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fpga: x4xx: add option for incremental Vivado build

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So far only the implementation after opt_run is affected by the changes.


Original-commit: 4c56b1b55ff3ae10561bd5efc83e3bb9a6a818d6
This commit is contained in:
Max Köhler
2024-03-12 16:03:23 -05:00
committed by Wade Fife
parent 275373c06b
commit e9700b2081
4 changed files with 28 additions and 12 deletions
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top/x400/Makefile
+5 -1
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@@ -82,6 +82,9 @@ DEFS += $(OPTIONS)
BUILD_SEED ?= 0
DEFS += BUILD_SEED=$(BUILD_SEED)
# Default value for incremental Vivado build is disabled.
INCR_BUILD ?= 0
# Defaults specific to the various targets:
X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_x4c_200_static_router.hex)
@@ -107,7 +110,7 @@ endif
TOP ?= x4xx
# vivado_build($1=Device, $2=Definitions, $3=Defaults)
vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3 INCR_BUILD=$(INCR_BUILD)
vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
# vivado_build($1=Device, $2=Option)
@@ -325,6 +328,7 @@ help: ##Show this help message.
##
##Supported Options
##-----------------
##INCR_BUILD=0 Use incremental Vivado build to speed up consecutive runs
##DRAM=0 Exclude DDR4 memory controller IP from the FPGA build.
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
top/x400/build_x4xx.tcl
+3 -3
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@@ -11,17 +11,17 @@ source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl
vivado_utils::initialize_project
# STEP#2: Run synthesis
vivado_utils::synthesize_design
vivado_utils::generate_post_synth_reports
# STEP#3: Run implementation strategy
set strategy [vivado_strategies::get_impl_preset "Performance_ExplorePostRoutePhysOpt"]
# Enable incremental build
dict set strategy "implementation.incremental" $::env(VIV_INCR_BUILD)
# Turn up uncertainty on 100Gb clocks(-quiet so if it fails because the clocks don't exist, it won't error)
set_clock_uncertainty 0.5 -quiet -setup [get_clocks txoutclk_out*]
# Vivado has been underestimating routing delays.
dict set strategy "place_design.directive" "ExtraNetDelay_high"
dict set strategy "place_design.directive" "ExtraNetDelay_high"
# Turn down uncertainty on 100Gb clocks
dict set strategy "route_design.pre_hook" {set_clock_uncertainty 0.0 -quiet -setup [get_clocks txoutclk_out*]}
vivado_strategies::implement_design $strategy