+ This documentation provides a description of the different register spaces available
+ for the USRP X4xx Open-Source FPGA target implementation, accessible through the
+ embedded ARM A53 processor in the RFSoC chip, and other UHD hosts.
+
The top is defined in HDL source file x410_rfdc_regs.v, x4xx.sv
+ This content is intended solely for use by core team members of the 'X410_FPGA' project.
+ Do not distribute or otherwise forward this content. If you believe you have acquired
+ access to this content in error, delete it immediately and notify the sender that you
+ are not intended to have access to this content.
+ This is the main AXI4-Lite master interface that the PS
+ exposes to the kernel to interact with the FPGA fabric.
+ There are multiple endpoints connected to this interface.
+
+
+ This port is defined in HDL source file x410_rfdc_regs.v.
+
+ This is the SPI1 interface
+ (see Zynq UltraScale+ Devices Register Reference)
+ of the PS.
+ With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.
+ The request format on SPI is defined as.
+ Write request:
+
+
1'b1 = write
+
15 bit address
+
32 bit data (MOSI)
+
8 bit processing gap
+
5 bit padding
+
1 bit ack
+
2 bit status
+
+ Read request:
+
+
1'b0 = read
+
15 bit address
+
8 bit processing gap
+
32 bit data (MISO)
+
5 bit padding
+
1 bit ack
+
2 bit status
+
+
+
+ This port is defined in HDL source file x410_rfdc_regs.v.
+
This is the map for the register space that the Processing System's
+M_AXI_HPM0_FPD port (AXI4 master interface) has access to.
+This port has a 40-bit address bus.
+ This is the map for the registers that the CORE_REGS window has access to
+ from the ARM_AXI_HPM0_FPD port.
+
+ The registers contained here conform the mboard-regs node that MPM uses
+ to manage general FPGA control/status calls, such as versioning,
+ timekeeper, GPIO, etc.
+
+ The following diagram shows how the communication bus interacts with the
+ modules in CORE_REGS.
+
+
+
+ Registers to control the SPI clock frequency of the CPLD interfaces.
+ The resulting clock frequency is calculated by .
+
+ Note that the PLL Reference Clock (PRC) is depending on the RF clocks.
+
+
+
+
+
+
+ This register is defined in HDL source file cpld_interface_regs.v.
+
+
+
+
+
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..8
+
+
Reserved
+
+
+
+
+
+
7..1
+
+
Reserved
+
+
+
+
+
+
0
+
+
IPASS_ENABLE_TRANSFER
+
If 1 enables the forwarding of iPass cable present signal to MB CPLD
+ using ctrlport requests. On change from 0 to 1 the current status is
+ transferred to the MB CPLD via SPI ctrlport request initially.
+ This register is defined in HDL source file x4xx_gpio_spi.v.
+
+
+
+
+ Starts a SPI transaction
+
+
+
+
Bits
Name
+
+
+
+
31..0w
+
+
SPI_DATA (initialvalue=0)
+
Payload to be sent for the SPI transaction. If the payload is shorter than 32 bits,
+ it must be aligned to the MSbs in this field. LSbs are ignored in this scenario.
+ Registers to control the GPIO buffer direction on the FPGA connected to
+ the DIO board. Further registers enable different sources to control and
+ read the GPIO lines as master. The following diagram shows how source
+ selection multiplexers are arranged, as well as an indicator for the
+ register that control them.
+
+ Make sure the GPIO lines between FPGA and GPIO board are not driven by
+ two drivers. Set the DIO registers in PS_CPLD_BASE_REGMAP appropriately.
+
+
+
+
+
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Sets whether the DIO signal line is driven by this register interface
+ or the user application.
+ 0 = user application is master, 1 = output of SW_DIO_CONTROL is master
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Set the direction of FPGA buffer connected to DIO ports on the DIO board.
+ Each bit represents one signal line. 0 = line is an input to the FPGA,
+ 1 = line is an output driven by the FPGA.
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls the values on each DIO signal line in case the line master is
+ set to PS in DIO_MASTER_REGISTER.
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls whether the DIO lines reflect the state of DIO_MASTER_REGISTER
+ or the radio blocks. 0 = DIO_MASTER_REGISTER,
+ 1 = Radio block output(DIO_OVERRIDE)
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls which radio block to use the ATR state from to determine the
+ state of the DIO lines.
+ 0 = Radio#0
+ 1 = Radio#1
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls which of the two available digital interfaces controls the DIO lines.
+ 0 = Digital interface from Radio#0,
+ 1 = Digital Interface from Radio#1.
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls whether the radio input to the DIO_SOURCE_REGISTER mux
+ connects to the ATR control or a Digital interface block. The output
+ of the mux controlled by this bit goes to DIO_SOURCE_REGISTER.
+ 0 = Drive the ATR state(RADIO_SOURCE_REGISTER), 1 = Drive
+ Digital interface block(Output of INTERFACE_DIO_SELECT).
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls which source is forwarded to the DIO_MASTER_REGISTER mux.
+ This configuration is applied independently for each DIO line.
+ 0 = MPM Ctrlport endpoint, 1 = PS Netlist DIO signal.
+
+ This is the map that the nixge driver uses in Ethernet DMA to
+ move data between the Processing System's architecture and the fabric.
+ This map is a combination of two main components: a Xilix AXI DMA engine
+ and some registers for MAC/PHY control.
+
+
+
+
+ This window is defined in HDL source file common_regs.v.
+
+
+
+
+ Refer to Xilinx' AXI DMA v7.1 IP product guide for further
+ information on this register map:
+ https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
+
+ This register is defined in HDL source file x4xx_global_regs.v.
+
+
+
+
+ Control register for clocking resources.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
PPS_BRC_DELAY
+
Number of base reference clock cycles from appearance of the PPS
+ rising edge to the occurrence of the aligned edge of base reference
+ clock and PLL reference clock at the sample PLL output. This number
+ is the sum of the actual value based on PLL_SYNC_DELAY (also
+ accumulate the fixed amount of clock cycles) and if any the number of
+ cycles the SPLL requires from issuing of the SYNC signal to the
+ aligned edge (with LMK04832 = 0).
+ The number written to this register has to be reduced by 1 due to
+ HDL implementation.
+
+
+
+
+
23..16
+
+
PLL_SYNC_DELAY
+
Due to the HDL implementation the rising edge of the SYNC signal for
+ the LMK04832 is generated 2 clock cycles after the PPS rising edge.
+ This delay can be further increased by setting this delay value
+ (e.g. PLL_SYNC_DELAY=3 will result in a total delay of 5 clock cycles).
+ In case two X400 devices are connected using the PPS and reference clock the master delay value needs to be 3 clock cycles
+ higher than the slave delay value to align the LMK sync edges in time.
Assertion triggers the SYNC signal generation for LMK04832 after the next appearance of the PPS rising edge.
+ There is no self reset on this trigger.
+ Keep this trigger asserted until PLL_SYNC_DONE is asserted.
+
+
+
+
+
7..6
+
+
Reserved
+
+
+
+
+
+
5..4
+
+
TRIGGER_IO_SELECT (initialvalue=TRIG_IO_INPUT)
+
IMPORTANT! SW must ensure any TRIG_IO consumers (downstream devices) ignore
+ and/or re-sync after enabling this port, since the output-enable is basically
+ asynchronous to the actual TRIG_IO driver.
+
+
+
+ The values for this bitfield are in the TRIG_IO_ENUM table.
+ (show herehide)
+
+
+
+
+
+
+
+
+
Value
+
Name
+
+
+
+
+
0
+
+
+
+ TRIG_IO_INPUT
+
+
+
+
+
+
+
+
1
+
+
+
+ TRIG_IO_PPS_OUTPUT
+
+
+
+
+
+
+ This enumerated type is defined in HDL source file x4xx_global_regs.v.
+
+
+
+
+
+
+
+
+
+
3r
+
+
REFCLK_LOCKED
+
RESERVED. This bit is not implemented on X4xx and reads as 0.
+
+
+
+
+
2
+
+
REF_SELECT
+
RESERVED. This bit is not implemented on X4xx and reads as 0.
+
+
+
+
+
1..0
+
+
PPS_SELECT (initialvalue=PPS_INT_25MHZ)
+
Select the source of the PPS signal.
+ For the internal generation the value depending on the base reference clock has to be chosen.
+ The external reference is taken from the PPS_IN pin and is independent of the base reference clock.
+
+
+
+ The values for this bitfield are in the PPS_ENUM table.
+ (show herehide)
+
+
+
+
+
+
+
+
+
Value
+
Name
+
+
+
+
+
0
+
+
+
+ PPS_INT_25MHZ
+
+
+
+
+
+
+
+
1
+
+
+
+ PPS_INT_10MHZ
+
+
+
+
+
+
+
+
2
+
+
+
+ PPS_EXT
+
+
+
+
+
+
+ This enumerated type is defined in HDL source file x4xx_global_regs.v.
+
+ This register is defined in HDL source file x4xx_global_regs.v.
+
+
+
+
+ Control registers for PPS generation.
+
+
+
+
Bits
Name
+
+
+
+
31
+
+
PPS_RC_ENABLED
+
Enables the PPS signal in radio clock domain. Please make sure that
+ the values of PPS_BRC_DELAY, PPS_PRC_DELAY, PRC_RC0_DIVIDER and
+ PRC_RC1_DIVIDER are set before enabling this bit. It is recommended
+ to disable the PPS for changes on the other values. Use a wait time of
+ at least 1 second before changing this value to ensure the values are
+ stable for the next PPS edge.
+
+
+
+
+
30..26
+
+
Reserved
+
+
+
+
+
+
25..0
+
+
PPS_PRC_DELAY
+
The number of PLL reference clock cycles from one aligned edge to the
+ desired aligned edge to issue the PPS in radio clock domain. This
+ delay is configurable to any aligned edge within a maximum delay of 1
+ second (period of PPS).
+ The value written to the register has to be reduced by 5 due to
+ HDL implementation.
+ This register is defined in HDL source file x4xx_global_regs.v.
+
+
+
+
+ Control registers for PPS clock crossing to the radio clock domain.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..21
+
+
Reserved
+
+
+
+
+
+
20..16
+
+
PRC_RC1_DIVIDER
+
Clock multiplier used to generate radio clock 1 from PLL reference clock.
+ The value written to the register has to follow the following formula:
+ PRC_RC1_DIVIDER = (RADIO_CLK_1 / PRC_CLK) * 2 - 2
+
+
+
+
+
15..8
+
+
Reserved
+
+
+
+
+
+
7..5
+
+
Reserved
+
+
+
+
+
+
4..0
+
+
PRC_RC0_DIVIDER
+
Clock multiplier used to generate radio clock 0 from PLL reference clock.
+ The value written to the register has to follow the following formula:
+ PRC_RC0_DIVIDER = (RADIO_CLK_0 / PRC_CLK) * 2 - 2
+ This register is defined in HDL source file x4xx_global_regs.v.
+
+
+
+
+ Status register for mfg_test functions.
+
+
+
+
Bits
Name
+
+
+
+
31..26
+
+
Reserved
+
+
+
+
+
+
25..0
+
+
MFG_TEST_FPGA_AUX_REF_FREQ
+
Report the time between rising edges on the FPGA_REF_CLK
+ input port in 40 MHz Clock ticks. If the count extends
+ to 1.2 seconds without an edge, the value reported is set
+ to zero.
+ This register is defined in HDL source file x4xx_gpio_atr.v.
+ It uses RegType GPIO_ATR_STATE which is
+ defined in HDL source file x4xx_gpio_atr.v.
+
+
+
+
+ Holds a single bit setting for GPIO lines in both ports for a particular ATR sate
+Describes GPIO behavior for the different ATR states. When ATR_OPTION
+ is set to use the DB states, TX and RX states for RF0 and RF1 are
+ combined to create a single vector. This creates 16 different
+ combinations, each with its own register. When ATR_OPTION is set to
+ classic ATR, offsets 0x00-0x03 in this register group will be driven
+ in accordance with the state of RF0, and offsets 0x04-0x07 will be
+ driven in accordance with the state of RF1.
+ CLASSIC ATR MAPPING: Idle[RF0:0x00; RF1:0x04], RX[RF0:0x01; RF1:0x05],
+ TX[RF0:0x02; RF1:0x06], FDX[RF0:0x03; RF1:0x07]
+
+ This register is defined in HDL source file x4xx_gpio_atr.v.
+
+
+
+
+ Controls the RF state mapping of each GPIO line when classic
+ ATR mode is active.
+
+
+
+
Bits
Name
+
+
+
+
31..28
+
+
Reserved
+
+
+
+
+
+
27..16
+
+
RF_SELECT_B (initialvalue=0)
+
Set which RF channel's state to reflect in the pins of
+ HDMI connector B when ATR_OPTION is set to classic ATR.
+ Controlled in a per-pin basis.
+ 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03)
+ 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)
+
+
+
+
+
15..12
+
+
Reserved
+
+
+
+
+
+
11..0
+
+
RF_SELECT_A (initialvalue=0)
+
Set which RF channel's state to reflect in the pins for
+ HDMI connector A when ATR_OPTION is set to classic ATR.
+ Controlled in a per-pin basis.
+ 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03)
+ 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)
+ This register is defined in HDL source file x4xx_gpio_atr.v.
+
+
+
+
+ Controls whether GPIO lines use the TX and RX state of an RF channel
+ (Classic ATR) or the daughterboard state the selector for the
+ ATR_STATE.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..8
+
+
Reserved
+
+
+
+
+
+
7..1
+
+
Reserved
+
+
+
+
+
+
0
+
+
ATR_OPTION (initialvalue=0)
+
Sets the scheme in which RF states in the radio will control GPIO
+ lines. 0 = DB state is used. RF states are combined and the
+ GPIO state is driven based on all 16 ATR_STATE registers.
+ 1 = Each RF channel has its separate ATR state(Classic ATR).
+ Use register CLASSIC_ATR_CONFIG to indicate the RF channel
+ to which each GPIO line responds to.
This register map is available using the PL CPLD SPI interface.
+All protocol masters controller by this register map are running with a clock frequency of 50 MHz.
+ This register is defined in HDL source file uhd_regs.v.
+
+
+
+
+
+
Definition of this register depends on Protocol
+
10GBE
+
READ - Status
+
+
0 = status_crc_error
+
1 = status_fragment_error
+
2 = status_txdfifo_ovflow
+
3 = status_txdfifo_udflow
+
4 = status_rxdfifo_ovflow
+
5 = status_rxdfifo_udflow
+
6 = status_pause_frame_rx
+
7 = status_local_fault
+
8 = status_remote_fault
+
+
WRITE - Ctl
+
+
0 = ctrl_tx_enable
+
+
100 GBE
+
READ - Status
+
+
0 = tx_ovfout - Sets if TX overflow reported by CMAC
+ (Stays set till MAC is reset). This is a fatal error
+
1 = tx_unfout - Sets if TX underflow reported by CMAC
+ (Stays set till MAC is reset). This is a fatal error
+
2 = stat_rx_aligned - goes high when CMAC has finished
+ alignment, and is ready to start reception of traffic.
+
3 = mac_dropped_packet - If the mac RX wants to push data(TVALID)
+ but upstream is trying to hold(TREADY)off we drop a packet.
+ Upstream circuitry should detect this when traffic is forked
+ between CHDR and CPU, so this bit will only set if there is a
+ HW design error.
+
4 = auto_config_done - This bit goes high when the auto_config
+ state machine finishes operation. It is very similiar to
+ stat_rx_alligned, but waits for extra writes which occur
+ after allignement to complete.
+
24:16 = pause_mask - readable version of pause_mask bellow.
+
+
WRITE - Ctl
+
+
0 = auto_enable - Defaults to ON after reset - Enables a
+ state machine that performs CMAC register writes to
+ bring up the MAC without SW intervention.
+
24:16 = pause_mask - A second layer of enables(the first being
+ register in the CMAC) on the pause_request mechanic. Bits
+ 7:0 of enable pause on PFC7:0. Bit 8 enables global pause
+ request (not priority controlled). The mask is used for TX
+ and RX.
+ This register is defined in HDL source file pl_cpld_regs.v.
+
+
+
+
+ This register returns (in YYMMDDHH format) the oldest revision
+ that is still compatible with this one. Compatible means that
+ registers or register bits may have been added, but not
+ modified or deleted (see OLDEST_CPLD_REVISION of CONSTANTS_REGMAP).
+
+ This register map is available from the PS via AXI and MPM endpoint.
+ Its size is 128K (17 bits). Only the 17 LSBs are used as address in this documentation.
+
+
+
+
+ This is a regmap to document the different ports that have access to the PS system memory.
+ Each port may have different restrictions on system memory. See the corresponding window
+ for details
+
+
+
+
+ This window is defined in HDL source file common_regs.v.
+
+
+
+
+ The HPC0 port of the PS is used for general purpose cache-coherent accesses
+ to the PS system memory. Different applications may use it for different
+ purposes. Its access is configured as follows:
+
+ This window is defined in HDL source file common_regs.v.
+
+
+
+
+ The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave
+ interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx.
+ Its access is configured as follows:
+
+ Registers to control the GPIO buffer direction on the DIO board connected to the FPGA.
+ Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers.
+ Set the direction in the FPGA's DIO register appropriately.
+
+
+
+
+
+
+ This register is defined in HDL source file ps_cpld_regs.v.
+
+
+
+
+ Set the direction of FPGA buffer connected to DIO ports on the DIO board.
+ Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA.
+
+ This register is defined in HDL source file ps_cpld_regs.v.
+
+
+
+
+ Register to control the PL part DB SPI connection and reset generation.
+ The DB connection is clocked with PLL reference clock. Ensure this clock is stable
+ and enabled before starting any SPI request.
+ The PLL reference clock can be disabled if both DB connections are disabled or inactive.
+ To enable the DB connection, enable clock with one write access and release
+ reset with the next write access.
+ To disable the DB connection, assert reset with one write access and
+ disable clocks with the next write access.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..22
+
+
Reserved
+
+
+
+
+
+
21w
+
+
ASSERT_RESET_DB1
+
Writing with this flag set asserts reset for DB 1 (overrides RELEASE_RESET_DB1)
+
+
+
+
+
20w
+
+
ASSERT_RESET_DB0
+
Writing with this flag set asserts reset for DB 0 (overrides RELEASE_RESET_DB0)
+
+
+
+
+
19..18
+
+
Reserved
+
+
+
+
+
+
17w
+
+
RELEASE_RESET_DB1
+
Writing with this flag set releases DB 1 reset. (may be overwritten by ASSERT_RESET_DB1)
+
+
+
+
+
16w
+
+
RELEASE_RESET_DB0
+
Writing with this flag set releases DB 0 reset. (may be overwritten by ASSERT_RESET_DB0)
+
+
+
+
+
15
+
+
Reserved
+
+
+
+
+
+
14w
+
+
DISABLE_PLL_REF_CLOCK
+
Writing with this flag set disables the PLL reference clock (overrides ENABLE_PLL_REF_CLOCK). Assert this flag to reconfigure the clock.
+
+
+
+
+
13w
+
+
DISABLE_CLOCK_DB1
+
Writing with this flag set disables DB 1 clock forwarding (overrides ENABLE_CLOCK_DB1)
+
+
+
+
+
12w
+
+
DISABLE_CLOCK_DB0
+
Writing with this flag set disables DB 0 clock forwarding (overrides ENABLE_CLOCK_DB0)
+
+
+
+
+
11
+
+
Reserved
+
+
+
+
+
+
10w
+
+
ENABLE_PLL_REF_CLOCK
+
Writing with this flag set enables the PLL reference clock. Assert this flag after PLL reference clock is stable. (may be overwritten by DISABLE_PLL_REF_CLOCK)
+
+
+
+
+
9w
+
+
ENABLE_CLOCK_DB1
+
Writing with this flag set enables DB 1 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB1)
+
+
+
+
+
8w
+
+
ENABLE_CLOCK_DB0
+
Writing with this flag set enables DB 0 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB0)
+
+
+
+
+
7..6
+
+
Reserved
+
+
+
+
+
+
5r
+
+
DB1_RESET_ASSERTED
+
Indicates that reset is asserted for DB 1.
+
+
+
+
+
4r
+
+
DB0_RESET_ASSERTED
+
Indicates that reset is asserted for DB 0.
+
+
+
+
+
3
+
+
Reserved
+
+
+
+
+
+
2r
+
+
PLL_REF_CLOCK_ENABLED
+
Indicates if the PLL reference clock for the PL interface is enabled.
+ This register is defined in HDL source file ps_cpld_regs.v.
+
+
+
+
+ This register returns (in YYMMDDHH format) the oldest revision
+ that is still compatible with this one. Compatible means that
+ registers or register bits may have been added, but not
+ modified or deleted (see OLDEST_CPLD_REVISION of CONSTANTS_REGMAP).
+
+ This register is defined in HDL source file ps_power_regs.v.
+
+
+
+
+ Controls the power supplies for the iPass connectors.
+
+
+
+
Bits
Name
+
+
+
+
31r
+
+
IPASS_POWER_FAULT1
+
Asserted signal indicates a power fault in power switch for iPass
+ connector 1. Sticky bit. Asserted on occurrence. Reset using
+ IPASS_CLEAR_POWER_FAULT1.
Asserted signal indicates a power fault in power switch for iPass
+ connector 0. Sticky bit. Asserted on occurrence. Reset using
+ IPASS_CLEAR_POWER_FAULT0.
+ Each radio's CtrlPort peripheral interface is divided into the
+ following memory spaces. Note that the CtrlPort peripheral interface
+ starts at offset 0x80000 in the RFNoC Radio block's register space.
+ The following diagram displays the distribution of the CtrlPort
+ interface to the different modules it interacts with.
+
+
+
+
+ These registers are used to upload and verify a new primary image to the
+ Max 10 FPGA on-chip flash when configured to support dual configuration
+ images. The steps below outline the process of verifying/preparing the
+ new image to be written, erasing the current image, writing the new
+ image, and verifying the new image was successfully written.
+
Prepare the data...
+
The Max 10 FPGA build should generate a *cfm0_auto.rpd
+ file The *.rpd file is a "raw programming
+ data" file holding all data related to the
+ configuration image (CFM0). There are two
+ important items to note regarding the addresses.
+ First the *rpd data uses byte addresses.
+ Second, the start/end addresses defined by
+ FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses
+
As a sanity check, verify the size of the raw
+ programming data for CFM0 correspond to the address
+ range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by
+ reading the values from FLASH_CFM0_START_ADDR_REG and
+ FLASH_CFM0_END_ADDR, subtract both values, add one and
+ multiply by four.
+
+
Having passed the sanity check the *.rpd data must
+ now be manipulated into the form required by Altera's
+ on-chip flash IP. Two operations must be performed.
+ First the data must be converted from bytes to 32-bit
+ words. Second the bit order must be reversed. This is
+ illustrated in in the following table which shows byte
+ address and data from the *.rpd file compared to the
+ word address and data to be written to the on-chip
+ flash.
+
+
.Map Addr
.Map Data
Flash Addr
Flash Data
+
0x2B800
0x01
0xAC00
0x8040C020
+
0x2B801
0x02
+
0x2B802
0x03
+
0x2B803
0x04
+
0x2B804
0x05
0xAC01
0xA060E010
+
0x2B805
0x06
+
0x2B806
0x07
+
0x2B807
0x08
+
+
+
The resulting set of flash address data pairs should
+ be used when writing FLASH_ADDR_REG and
+ FLASH_WRITE_DATA_REG to update the CFM0 image.
+ However, prior to writing the new image the old image
+ must be erased.
+
+
+
+
Erase the current primary flash image...
+
Read FLASH_STATUS_REG and verify no error bits are
+ asserted and that all read, write, and erase operations
+ are idle.
+
Disable write protection of the flash by strobing the
+ FLASH_DISABLE_WP_STB bit of FLASH_CONTROL_REG.
+
+
Verify write protection is disabled and no errors are
+ present by reading FLASH_STATUS_REG.
+
Initiate the erase operation by setting
+ FLASH_ERASE_SECTOR and strobing FLASH_ERASE_STB of
+ FLASH_CONTROL_REG.
+
Poll the FLASH_ERASE_IDLE bit of
+ FLASH_STATUS_REG until it de-asserts indicating the
+ erase operation is complete, then verify the operation
+ was successful by checking that the FLASH_ERASE_ERR
+ bit is de-asserted. Erase operations are expected to
+ take a maximum of 350 msec. Upon completion of the erase
+ operation write protection will remain disabled.
+
+
Erase additional sectors as required (see
+ FLASH_ERASE_SECTOR for details) by restarting with first
+ step.
+
+
+
Write the new primary flash image...
+
Read FLASH_STATUS_REG and verify no error bits are
+ asserted, all read, write, and erase operations are
+ idle, and write protection is disabled.
+
Set the target address for the write to the Max 10
+ on-chip flash by writing value from
+ FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.
+
Set the data to be written to this address by writing
+ the new 32-bit word of the new image to
+ FLASH_WRITE_DATA_REG.
+
Initiate the write by strobing FLASH_WRITE_STB of
+ FLASH_CONTROL_REG.
+
Poll the FLASH_WRITE_IDLE bit of
+ FLASH_STATUS_REG until it de-asserts indicating the
+ write operation is complete, then verify the operation
+ was successful by checking that the FLASH_WRITE_ERR
+ bit is de-asserted. Write operations are expected to
+ take a maximum of 550 usec.
+
Upon completion of the write operation return to step
+ 2, incrementing the target address by one, and writing
+ the next 32-bit word to Max10FlashWriteDatReg. If this
+ was the last write, indicated by writing to
+ FLASH_PRIMARY_IMAGE_END_ADDR, proceed to the next step
+ to enable write protection.
+
After writing the new image enable write protection
+ by strobing the FLASH_ENABLE_WP_STB bit of
+ FLASH_CONTROL_REG.
+
+
+
Verify the new primary flash image...
+
Read FLASH_STATUS_REG and verify no error bits are
+ asserted and that all read, write, and erase operations
+ are idle.
+
Set the target address for the read in the Max 10
+ on-chip flash by writing value from
+ FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.
+
Initiate the read by strobing FLASH_READ_STB of
+ FLASH_CONTROL_REG.
+
Poll the FLASH_READ_IDLE bit of
+ FLASH_STATUS_REG until it de-asserts indicating the
+ read operation is complete, then verify the operation
+ was successful by checking that the FLASH_READ_ERR
+ bit is de-asserted. There is no guidance on exactly how
+ long reads take to complete, but they are expected to be
+ fairly quick. A very conservative timeout on this
+ polling would be similar to that used for write
+ operations.
+
Upon completion of the read operation the resulting
+ data returned by the on-chip flash will be available in
+ Max10FlashReadDatReg. Read this register, compare to
+ expected value previously written, and ensure they
+ match.
+
Return to step 2, incrementing the target
+ address by one. If this was the last read verification
+ is complete and no further action is required.
+
+
+
After the flash has been erased, programmed, and verified, a power
+ cycle is required for the new image to become active.
+
+ These values are the start and end address of the CFM image flash
+ sector from Intel's On-Chip Flash IP Generator.
+ Be aware that three different values exist per each of the two
+ supported MAX10 variants: 10M04 and 10M08
+ Note that the values given in the IP generator are byte based where
+ the values of this enum are U32 based (divided by 4).
+
+
+ This register is defined in HDL source file reconfig_engine.v.
+
+
+
+
+
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..17
+
+
Reserved
+
+
+
+
+
+
16
+
+
FLASH_MEM_INIT_ENABLED
+
This bit is asserted when the flash can hold an image with memory
+ initialization.
+
+
+
+
+
15..14
+
+
Reserved
+
+
+
+
+
+
13
+
+
FLASH_WRITE_ERR
+
This bit is asserted when write operation fails. Clear this error
+ by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In
+ the event of a write error...
+
the primary configuration image may be corrupted, and
+ power cycling the board may result unknown behavior.
+
write protection of the flash will automatically be
+ re-enabled.
+
attempts to disable write protection will be ignored.
+
attempts to read/write/erase the flash will be ignored.
+
+
+
+
+
12
+
+
FLASH_WRITE_IDLE
+
This bit is de-asserted when a write operation is in progress. Poll
+ this bit after strobing the FLASH_WRITE_STB bit of
+ FLASH_CONTROL_REG to determine when the write operation has
+ completed, then check the FLASH_WRITE_ERR bit to verify the
+ operation was successful.
+
+
+
+
+
11..10
+
+
Reserved
+
+
+
+
+
+
9
+
+
FLASH_ERASE_ERR
+
This bit is asserted when an erase operation fails. Clear this
+ error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In
+ the event of an erase error...
+
the primary configuration image may be corrupted, and
+ power cycling the board may result in unknown behavior.
+
write protection of the flash will automatically be
+ re-enabled.
+
attempts to disable write protection will be ignored.
+
attempts to read/write/erase the flash will be ignored.
+
+
+
+
+
8
+
+
FLASH_ERASE_IDLE
+
This bit is de-asserted when an erase operation is in progress. Poll
+ this bit after strobing the FLASH_ERASE_STB bit of
+ FLASH_CONTROL_REG to determine when the erase operation has
+ completed, then check the FLASH_ERASE_ERR bit to verify the
+ operation was successful.
+
+
+
+
+
7..6
+
+
Reserved
+
+
+
+
+
+
5
+
+
FLASH_READ_ERR
+
This bit is asserted when a read operation fails. Clear this error
+ by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the
+ event of a read error...
+
the data in FLASH_READ_DATA_REG is invalid.
+
attempts to disable write protection will be ignored.
+
attempts to read/write/erase the flash will be ignored.
+
+
+
+
+
4
+
+
FLASH_READ_IDLE
+
This bit is de-asserted when a read operation is in progress. Poll
+ this bit after strobing the FLASH_READ_STB bit of
+ FLASH_CONTROL_REG to determine when the read operation has
+ completed, then check the FLASH_READ_ERR bit to verify the
+ operation was successful.
+
+
+
+
+
3..1
+
+
Reserved
+
+
+
+
+
+
0
+
+
FLASH_WP_ENABLED
+
This bit is asserted when the flash is write protected and
+ de-asserted when write protection is disabled.
+
Write protection must be enabled prior to performing read
+ operations.
+
Write protection must be disabled prior to performing write and
+ erase operations.
+ This register is defined in HDL source file reconfig_engine.v.
+
+
+
+
+
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..11
+
+
Reserved
+
+
+
+
+
+
10w
+
+
CLEAR_FLASH_ERASE_ERROR_STB (Strobe)
+
Strobe this bit to clear an erase error.
+
+
+
+
+
9w
+
+
CLEAR_FLASH_WRITE_ERROR_STB (Strobe)
+
Strobe this bit to clear a write error.
+
+
+
+
+
8w
+
+
CLEAR_FLASH_READ_ERROR_STB (Strobe)
+
Strobe this bit to clear a read error.
+
+
+
+
+
7..5w
+
+
FLASH_ERASE_SECTOR (Strobe)
+
Defines the sector to be erased. Has to be set latest with the
+ write access which starts the erase operation by strobing
+ FLASH_ERASE_STB.
+ With 10M04 variants, if the flash is configured to support memory
+ initialization (see FLASH_MEM_INIT_ENABLED flag) the sectors 2
+ to 4 have to be erased. If the flag is not asserted only sector 4
+ has to be erased.
+ With 10M08 variants, the sectors to be erased are 3 to 5 when
+ using memory initialization or only sector 5 otherwise.
+
+
+
+
+
4w
+
+
FLASH_ERASE_STB (Strobe)
+
Strobe this bit to erase the primary Max10 configuration image
+ (CFM0).
+
Prior to strobing this bit verify no other write or erase
+ operations are in progress, write protection is disabled, and no
+ error bits are asserted by reading FLASH_STATUS_REG.
+
Attempts to erase the primary image while other write or erase
+ operations are in progress will be ignored.
+
Attempts to erase the primary image when write protection is
+ enabled will be ignored.
+
Strobing this bit and FLASH_WRITE_STB simultaneously will
+ result both the erase and the write operation being ignored, both
+ corresponding error bits being set, and write protection being
+ re-enabled.
+
After strobing this bit poll the FLASH_ERASE_IDLE and
+ FLASH_ERASE_ERR bits of FLASH_STATUS_REG to determine when
+ the erase operation is complete and if it was successful.
+
+
+
+
+
3w
+
+
FLASH_WRITE_STB (Strobe)
+
Strobe this bit to write the data contained in
+ FLASH_WRITE_DATA_REG to the flash address identified in
+ FLASH_ADDR_REG.
+
The flash must be erased before writing new data.
+
Prior to strobing this bit verify write protection is
+ disabled, no other write or erase operations are in progress, and
+ no error bits are asserted by reading FLASH_STATUS_REG.
+
Attempts to write data while other write or erase operations
+ are in progress will be ignored.
+
Attempts to write data with write protection enabled will be
+ ignored.
+
Strobing this bit and FLASH_ERASE_STB simultaneously will
+ result in both the write and erase operation being ignored,
+ both corresponding error bits being set, and write protection
+ being re-enabled.
+
After strobing this bit poll theMax10FlashWriteIdle and
+ FLASH_WRITE_ERR bits of FLASH_STATUS_REG to determine when
+ the write operation is complete and if it was successful.
+
+
+
+
+
2w
+
+
FLASH_READ_STB (Strobe)
+
Strobe this bit to read data from the flash address identified in
+ FLASH_ADDR_REG.
+
Prior to strobing this bit verify no read, write, or erase
+ operations are in progress, no error bits are asserted, and
+ write protection is enabled by reading FLASH_STATUS_REG.
+
Attempts to read data while other operations are in progress
+ or while write protection is disabled will be ignored.
+
After strobing this bit poll the FLASH_READ_IDLE and
+ FLASH_READ_ERR bits of FLASH_STATUS_REG to determine when
+ the read operation is complete and if it was successful.
+
Upon successful completion the data read from flash will be
+ available in FLASH_READ_DATA_REG.
+
+
+
+
+
1w
+
+
FLASH_DISABLE_WP_STB (Strobe)
+
Strobe this bit to disable write protection to the section of the
+ Max 10 on-chip flash storing the primary configuration image
+ (CFM0).
+
Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to
+ determine the current state of write protection.
+
Prior to strobing this bit verify no read operations are in
+ progress and no error bits are asserted by reading
+ FLASH_STATUS_REG.
+
Attempts to disable write protection while a read is in
+ progress will be ignored.
+
Attempts to disable write protection will be ignored if
+ this bit is strobed simultaneously with either FLASH_READ_STB
+ or FLASH_ENABLE_WP_STB.
+
Write protection must be disabled prior to performing erase or
+ write operations.
+
Upon completion of erase/write operations write protection
+ will remain disabled. When not actively erasing or writing a new
+ image write protection should be enabled to avoid data
+ corruption.
+
+
+
+
+
0w
+
+
FLASH_ENABLE_WP_STB (Strobe)
+
Strobe this bit to enable write protection to the section of the
+ Max 10 on-chip flash storing the primary configuration image
+ (CFM0).
+
Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to
+ determine the current state of write protection.
+
Prior to strobing this bit verify no write or erase operations
+ are in progress and no error bits are asserted by reading
+ FLASH_STATUS_REG.
+
Attempts to enable write protection while erase or write
+ operations are in progress will be ignored.
+
Write protection must be enabled prior to performing
+ read operations.
+
Write protection should be enabled after completing
+ write or erase operations to prevent data corruption.
+ This register is defined in HDL source file reconfig_engine.v.
+
+
+
+
+
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..17
+
+
Reserved
+
+
+
+
+
+
16..0
+
+
FLASH_ADDR
+
This field holds the target address for the next read or
+ write operation. Set this field prior to strobing the
+ FLASH_WRITE_STB and FLASH_READ_STB bits of
+ FLASH_CONTROL_REG. Valid addresses are defined by the
+ FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration.
+ This window is defined in HDL source file x410_rfdc_regs.v.
+
+
+
+
+ Register space for controlling the data clock MMCM instance
+ within the RFDC block design.
+ Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the
+ regiter space description in chapter 2.
+ (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)
+
+ This register is defined in HDL source file x410_rfdc_regs.v.
+ It uses RegType RF_RESET_CONTROL_REGTYPE which is
+ defined in HDL source file common_regs.v.
+
+
+
+
+ Control register for the RF reset controller.
+ Verify the FSM ID before polling starting any reset sequence.
+ To use the SW reset triggers: Wait until DB*_DONE is de-asserted.
+ Assert either the *_RESET or *_ENABLE bitfields.
+ Wait until DB*_DONE is asserted to release the trigger.
+ The DB*_DONE signal should then de-assert.
+ Note: The *_DB1 constants are not used in the HDL, their purpose is
+ merely for documentation.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..10
+
+
Reserved
+
+
+
+
+
+
9
+
+
DAC_ENABLE
+
Write a '1' to this bit to trigger the enable sequence for
+ the daughterboard 0 DAC chain. Write a '0' once
+ db0_dac_seq_done is asserted.
+
+
+
+
+
8
+
+
DAC_RESET
+
Write a '1' to this bit to trigger a reset for the
+ daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done
+ is asserted.
+
+
+
+
+
7..6
+
+
Reserved
+
+
+
+
+
+
5
+
+
ADC_ENABLE
+
Write a '1' to this bit to trigger the enable sequence for
+ the daughterboard 0 ADC chain. Write a '0' once
+ db0_adc_seq_done is asserted.
+
+
+
+
+
4
+
+
ADC_RESET
+
Write a '1' to this bit to trigger a reset for the
+ daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done
+ is asserted.
+
+
+
+
+
3..1
+
+
Reserved
+
+
+
+
+
+
0
+
+
FSM_RESET
+
Write a '1' to this bit to reset the RF reset controller.
+ Write a '0' once db0_fsm_reset_done asserts.
+ This register is defined in HDL source file x410_rfdc_regs.v.
+ It uses RegType RF_RESET_STATUS_REGTYPE which is
+ defined in HDL source file common_regs.v.
+
+
+
+
+ Status register for the RF reset controller.
+ Verify the FSM ID before polling starting any reset sequence.
+ Refer to RF*_RESET_CONTROL_REG for instructions on how to use
+ the status bits in this register.
+ Note: The *_DB1 constants are not used in the HDL, their purpose is
+ merely for documentation.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..12
+
+
Reserved
+
+
+
+
+
+
11
+
+
DAC_SEQ_DONE
+
This bit asserts ('1') when the DB0 DAC chain reset sequence
+ is completed. The bitfield deasserts ('0') after
+ deasserting the issued triggered (enable or reset).
+
+
+
+
+
10..8
+
+
Reserved
+
+
+
+
+
+
7
+
+
ADC_SEQ_DONE
+
This bit asserts ('1') when the DB0 ADC chain reset sequence
+ is completed. The bitfield deasserts ('0') after
+ deasserting the issued triggered (enable or reset).
+
+
+
+
+
6..4
+
+
Reserved
+
+
+
+
+
+
3
+
+
FSM_RESET_DONE
+
This bit asserts ('1') when the DB0 RF reset controller FSM
+ reset sequence is completed. The bitfield deasserts ('0')
+ after deasserting db0_fsm_reset.
+ This register is defined in HDL source file x410_rfdc_regs.v.
+ It uses RegType RF_AXI_STATUS_REGTYPE which is
+ defined in HDL source file common_regs.v.
+
+
+
+
+ Status register for the RF AXI-Stream interfaces.
+ Note: The *_DB1 constants are not used in the HDL, their purpose is
+ merely for documentation.
+
+
+
+
Bits
Name
+
+
+
+
31..30
+
+
USER_ADC_TREADY_DB1
+
This bitfield is wired to the user's ADC (DB1) AXI-Stream
+ TReady handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
29..28
+
+
USER_ADC_TVALID_DB1
+
This bitfield is wired to the user's ADC (DB1) AXI-Stream
+ TValid handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
27..26
+
+
RFDC_ADC_I_TVALID_DB1
+
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
+ TValid handshake signals (I portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
25..24
+
+
RFDC_ADC_Q_TVALID_DB1
+
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
+ TValid handshake signals (Q portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
23..22
+
+
RFDC_ADC_I_TREADY_DB1
+
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
+ TReady handshake signals (I portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
21..20
+
+
RFDC_ADC_Q_TREADY_DB1
+
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
+ TReady handshake signals (Q portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
19..18
+
+
RFDC_DAC_TVALID_DB1
+
This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
+ TValid handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
17..16
+
+
RFDC_DAC_TREADY_DB1
+
This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
+ TReady handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
15..14
+
+
USER_ADC_TREADY
+
This bitfield is wired to the user's ADC (DB0) AXI-Stream
+ TReady handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
13..12
+
+
USER_ADC_TVALID
+
This bitfield is wired to the user's ADC (DB0) AXI-Stream
+ TValid handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
11..10
+
+
RFDC_ADC_I_TVALID
+
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
+ TValid handshake signals (I portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
9..8
+
+
RFDC_ADC_Q_TVALID
+
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
+ TValid handshake signals (Q portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
7..6
+
+
RFDC_ADC_I_TREADY
+
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
+ TReady handshake signals (I portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
5..4
+
+
RFDC_ADC_Q_TREADY
+
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
+ TReady handshake signals (Q portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
3..2
+
+
RFDC_DAC_TVALID
+
This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
+ TValid handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
1..0
+
+
RFDC_DAC_TREADY
+
This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
+ TReady handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+ This register is defined in HDL source file x410_rfdc_regs.v.
+ It uses RegType FABRIC_DSP_REGTYPE which is
+ defined in HDL source file common_regs.v.
+
+
+
+
+ This register provides information to the driver on the type
+ of DSP that is instantiated in the fabric.
+ The X410 platform supports multiple RF daughterboards, each requiring
+ a different fabric RF DSP chain that works with specific RFDC settings.
+ Each bandwidth DSP chain has a unique identifier (BW in MHz), this
+ information is conveyed in this register to let the driver
+ configure the RFDC with the proper settings.
+ Also, channel count for the DSP module is included.
+ Note: The *_DB1 constants are not used in the HDL, their purpose is
+ merely for documentation.
+
+
+
+
Bits
Name
+
+
+
+
31..20
+
+
FABRIC_DSP_BW (initialvalue=FABRIC_DSP_BW_NONE)
+
Fabric DSP BW in MHz for both daughterboards.
+
+
+
+ The values for this bitfield are in the FABRIC_DSP_BW_ENUM table.
+ (show herehide)
+
+
+
+
+
+
+
+
+
Value
+
Name
+
+
+
Dec
+
Hex
+
+
+
+
+
0
+
0x000
+
+
+
+ FABRIC_DSP_BW_NONE
+
+
+
+
+
+
+
+
100
+
0x064
+
+
+
+ FABRIC_DSP_BW_100M
+
+
+
+
+
+
+
+
200
+
0x0C8
+
+
+
+ FABRIC_DSP_BW_200M
+
+
+
+
+
+
+
+
400
+
0x190
+
+
+
+ FABRIC_DSP_BW_400M
+
+
+
+
+
+
+
+
1000
+
0x3E8
+
+
+
+ FABRIC_DSP_BW_FULL
+
+
+
+
+
+
+ This enumerated type is defined in HDL source file common_regs.v.
+
+ This register is defined in HDL source file x410_rfdc_regs.v.
+
+
+
+
+ This register enables calibration data in the DAC data path for each of the
+ four channels. Each of these bits is normally '0'. When written '1', DAC data
+ for the corresponding channel will be constantly driven with the contents of
+ the CALIBRATION_DATA register.
+
+ This register is defined in HDL source file x410_rfdc_regs.v.
+
+
+
+
+ This register shows threshold status for the ADCs. Each bit reflects the
+ RFDC's real-time ADC status signals, which will assert when the ADC input
+ signal exceeds the programmed threshold value. The status will remain
+ asserted until cleared by software.
+ The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is
+ the location of the tile in the converter column and ZZ is either 01 (the
+ lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
+ See also the Xilinx document PG269.
+
+ This register is defined in HDL source file x410_rfdc_regs.v.
+ It uses RegType RFDC_INFO_MEMTYPE which is
+ defined in HDL source file rfdc_info_pkg.sv.
+
+
+
+
+ This register provides information for one ADC/DAC within the RFSoC and its RFDC
+ configuration. There is further information on the RFNoC index of this channel.
+ The register is defined as a SystemVerilog typedef and consumed by MPM using the RFDC
+ Python register interface.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..12
+
+
Reserved
+
+
+
+
+
+
11
+
+
IS_ADC
+
If the converter is an ADC this bit is set. Otherwise it is an DAC.
+
+
+
+
+
10
+
+
DB
+
DB index.
+
+
+
+
+
9..8
+
+
CHANNEL
+
Index of the RFNoC channel per DB.
+
+
+
+
+
7..6
+
+
RESERVED2
+
Reserved for later use.
+
+
+
+
+
5..4
+
+
TILE
+
Zero based tile offset of the FPGA.
+ For DAC index i equals to FPGA tile 228+i.
+ For ADC index i equals to FPGA tile 224+i.
+
+
+
+
+
3..2
+
+
BLOCK
+
Index of the ADC/DAC within the FPGA tile.
+
+
+
+
+
1..0
+
+
BLOCK_MODE
+
The state of this ADC/DAC.
+
+
+
+ The values for this bitfield are in the RFDC_BLOCK_INFO_ENUM table.
+ (show herehide)
+
+
+
+
+
+
+
+
+
Value
+
Name
+
+
+
Dec
+
Hex
+
+
+
+
+
0
+
0x0
+
+
+
+ ENABLED
+
+
+
+
+
+
+
+
3
+
0x3
+
+
+
+ DISABLED
+
+
+
+
+
+
+ This enumerated type is defined in HDL source file rfdc_info_pkg.sv.
+
+ This register is defined in HDL source file x410_rfdc_regs.v.
+ It uses RegType RFDC_INFO_REGTYPE which is
+ defined in HDL source file common_regs.v.
+
+
+
+
+ This register provides information about how the RFDC is connected to
+ the rest of the fabric.
+ Specifically, between the actual RFDC and the RFNoC infrastructure,
+ there may be additional resampling (if the RFDC resampler cannot handle
+ all the resampling itself) and it is important to know how wide the
+ connection from the RFDC gearbox FIFO to the rest of the design is.
+ Note: The *_DB1 constants are not used in the HDL, their purpose is
+ merely for documentation.
+
+
+
+
Bits
Name
+
+
+
+
31..26
+
+
Reserved
+
+
+
+
+
+
25..23
+
+
RFDC_INFO_SPC_TX_DB1 (initialvalue=1)
+
Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 1.
+
+
+
+
+
22..20
+
+
RFDC_INFO_SPC_RX_DB1 (initialvalue=1)
+
Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 1.
+
+
+
+
+
19..16
+
+
RFDC_INFO_XTRA_RESAMP_DB1 (initialvalue=1)
+
Additional resampling happening outside the RFDC for daughterboard 0.
+
+
+
+
+
15..10
+
+
Reserved
+
+
+
+
+
+
9..7
+
+
RFDC_INFO_SPC_TX (initialvalue=1)
+
Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 0.
+
+
+
+
+
6..4
+
+
RFDC_INFO_SPC_RX (initialvalue=1)
+
Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 0.
+
+
+
+
+
3..0
+
+
RFDC_INFO_XTRA_RESAMP (initialvalue=1)
+
Additional resampling happening outside the RFDC for daughterboard 0.
+ This register is defined in HDL source file rfdc_timing_control.v.
+
+
+
+
+ Gearbox reset control register.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..8
+
+
Reserved
+
+
+
+
+
+
7..2
+
+
Reserved
+
+
+
+
+
+
1w
+
+
DAC_RESET (Strobe)
+
This reset is for the gearbox on the DAC data path that is used to
+ move data from one clock domain to another outside the RFDC. Write
+ a 1 to this bit to send a reset pulse to the DAC gearbox.
+
+
+
+
+
0w
+
+
ADC_RESET (Strobe)
+
This reset is for the gearbox on the ADC data path that is used to
+ move data from one clock domain to another outside the RFDC. Write
+ a 1 to this bit to send a reset pulse to the ADC gearbox.
For information about the register content and the way to interact with the core see the
+documentation
+of the SPI master from opencores used internally.
+
The core is configured to operate with 16 slave signal signals, up to 128 bits per transmission and 8 bit clock divider.
+Only 64 bits of data are available via this register interface.
+
For the different SPI modes use the following table to derive the bits in CONTROL register. Only option 0 (CPOL=0, CPHA=0) has been tested.
+ This register is defined in HDL source file uhd_regs.v.
+
+
+
+
+
+
+
+
+
+
Bits
Name
+
+
+
+
31..16
+
+
pause_clear
+
+
If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause.
+Pause clear must be less than pause set or terrible things will happen.
+The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only
+used with 100Gb ethernet
+
+
+
+
+
15..0
+
+
pause_set
+
+
If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only
+used with 100Gb ethernet
+ Daughterboard GPIO interface.
+ For guidance on when to update these revision numbers,
+ please refer to the register map documentation accordingly:
+
+ This enum contains indexes for all the components in the X410
+ (both common and app-specific) which version information is
+ desired to be available for compatibility tracking purposes.
+
+
Description
Index range
Max # of components
+
Common components
0 to 23
24
+
UHD-specific components
24 to 43
20
+
LV-specific components
44 to 63
20
+
+
+
+
+
Value
+
Name
+
+
+
+
+
0
+
+
+
+ FPGA_VERSION_INDEX
+
+
+
+
+
+
+
+
1
+
+
+
+ CPLD_IFC_INDEX
+
+
+
+
+
+
+
+
2
+
+
+
+ DB0_RF_CORE_INDEX
+
+
+
+
+
+
+
+
3
+
+
+
+ DB1_RF_CORE_INDEX
+
+
+
+
+
+
+
+
4
+
+
+
+ DB0_GPIO_IFC_INDEX
+
+
+
+
+
+
+
+
5
+
+
+
+ DB1_GPIO_IFC_INDEX
+
+
+
+
+
+
+ This enumerated type is defined in HDL source file x4xx_versioning_regs.v.
+
+ This register is defined in HDL source file x4xx_versioning_regs.v.
+ It uses RegType VERSION_TYPE which is
+ defined in HDL source file x4xx_versioning_regs.v.
+
+
+
+
+ Component's current version.
+ This register contains the current component's version implemented in HDL.
+ The current version shall be used to detect a component being too
+ old for the driver/software:
+ SW oldest compatible version > Component's current version --> Component is too old.
+
+
+
+
Bits
Name
+
+
+
+
31..23
+
+
MAJOR (initialvalue=0)
+
Major number (max = 511): an increase reflects a breaking change.
+ IMPORTANT!MAJOR must always remain in sync between the component's
+ CURRENT_VERSION and OLDEST_COMPATIBLE_VERSION registers.
a new feature is added to the component, which does not conflict with the driver.
+
minor implementation changes were made to the component which are worth tracking.
+
the component has added new bitfields/registers that do not require software interaction
+ (i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to
+ previously undefined bits).
+
Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
+ but that should not impact the component's behavior
+ Eventually, this number is intended to be automatically incremented for any new build.
+ This register is defined in HDL source file x4xx_versioning_regs.v.
+ It uses RegType VERSION_TYPE which is
+ defined in HDL source file x4xx_versioning_regs.v.
+
+
+
+
+ Component's oldest compatible version.
+ This register contains the oldest compatible component's version, that is the oldest
+ component's implementation that is compatible with the current implementation.
+ The oldest compatible version shall be used to detect a component being too
+ new for the driver/software:
+ SW current version < Component's oldest compatible version --> Component is too new.
+
+
+
+
Bits
Name
+
+
+
+
31..23
+
+
MAJOR (initialvalue=0)
+
Major number (max = 511): an increase reflects a breaking change.
+ IMPORTANT!MAJOR must always remain in sync between the component's
+ CURRENT_VERSION and OLDEST_COMPATIBLE_VERSION registers.
a new feature is added to the component, which does not conflict with the driver.
+
minor implementation changes were made to the component which are worth tracking.
+
the component has added new bitfields/registers that do not require software interaction
+ (i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to
+ previously undefined bits).
+
Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
+ but that should not impact the component's behavior
+ Eventually, this number is intended to be automatically incremented for any new build.
+ This register is defined in HDL source file x4xx_versioning_regs.v.
+ It uses RegType TIMESTAMP_TYPE which is
+ defined in HDL source file x4xx_versioning_regs.v.
+
+
+
+
+ Component's versions update time.
+ This register provides the time stamp for the last modification to
+ the component's versions (current & oldest compatible).
+ The time stamp is provided in hexadecimal format: 0xYYMMDDHH.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
YY
+
This is the year number after 2000 (e.g. 2019 = 0x19).
+ This register is defined in HDL source file x4xx_versioning_regs.v.
+ It uses RegType RESERVED_TYPE which is
+ defined in HDL source file x4xx_versioning_regs.v.
+
-
-
\ No newline at end of file
diff --git a/top/x400/doc/X410/X410_FPGA_right.htm b/top/x400/doc/X410/X410_FPGA_right.htm
deleted file mode 100644
index 2c46486..0000000
--- a/top/x400/doc/X410/X410_FPGA_right.htm
+++ /dev/null
@@ -1,26316 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
X410_FPGA
- This documentation provides a description of the different register spaces available
- for the USRP X4xx Open-Source FPGA target implementation, accessible through the
- embedded ARM A53 processor in the RFSoC chip, and other UHD hosts.
-
The top is defined in HDL source file x410_rfdc_regs.v, x4xx.v.
- This section lists all common Processing System ports through
- which the register maps in this project are accessed. Each input
- port to the fabric will point to a regmap.
-
-
-This is the main AXI4-Lite master interface that the PS
- exposes to the kernel to interact with the FPGA fabric.
- There are multiple endpoints connected to this interface.
-
-
-
-
- This port is defined in HDL source file x410_rfdc_regs.v.
-
-
-This is the SPI1 interface
- (see Zynq UltraScale+ Devices Register Reference)
- of the PS.
- With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.
- The request format on SPI is defined as.
- Write request:
-
-
1'b1 = write
-
15 bit address
-
32 bit data (MOSI)
-
8 bit processing gap
-
5 bit padding
-
1 bit ack
-
2 bit status
-
- Read request:
-
-
1'b0 = read
-
15 bit address
-
8 bit processing gap
-
32 bit data (MISO)
-
5 bit padding
-
1 bit ack
-
2 bit status
-
-
-
-
-
- This port is defined in HDL source file x410_rfdc_regs.v.
-
-
-
-
-
-
-
-
-
-
-
AXI_HPM0_REGMAP
-
-
This is the map for the register space that the Processing System's
-M_AXI_HPM0_FPD port (AXI4 master interface) has access to.
-This port has a 40-bit address bus.
- Basic registers containing version and capabilities information.
-
-
-
-
CONSTANTS_ENUM Enumeration
-This enumeration is used to create the constants held in the basic registers.
-
-
-
-
Value
-
Name
-
-
-
-
-
-
Dec
-
-
Hex
-
-
-
-
-
-
173157671
-
-
0x0A522D27
-
-
-
PS_CPLD_SIGNATURE
-
-
-
-
-
-
-
-
538059028
-
-
0x20122114
-
-
-
OLDEST_CPLD_REVISION
-
-
-
-
-
-
-
-
570950676
-
-
0x22080414
-
-
-
CPLD_REVISION
-
-
-
-
-
-
-
-
1071406151
-
-
0x3FDC5C47
-
-
-
PL_CPLD_SIGNATURE
-
-
-
-
-
-
-
-
- This enumerated type is defined in HDL source file mb_cpld.v.
-
-
-
-
-
-
-
-
-
-
-
CORE_REGS_REGMAP
- This is the map for the registers that the CORE_REGS window has access to
- from the ARM_AXI_HPM0_FPD port.
-
- The registers contained here conform the mboard-regs node that MPM uses
- to manage general FPGA control/status calls, such as versioning,
- timekeeper, GPIO, etc.
-
- The following diagram shows how the communication bus interacts with the
- modules in CORE_REGS.
-
This register is defined in HDL source file cpld_interface_regs.v.
-
-
-
-
-
-Read/write register for general software use.
-
-
-
-
-
-
-
-
CPLD_SPI_CONTROL_REGS
- Registers to control the SPI clock frequency of the CPLD interfaces.
- The resulting clock frequency is calculated by .
-
- Note that the PLL Reference Clock (PRC) is depending on the RF clocks.
-
This register is defined in HDL source file cpld_interface_regs.v.
-
-
-
-
-
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..8
-
-
Reserved
-
-
-
-
-
-
-
7..1
-
-
Reserved
-
-
-
-
-
-
-
0
-
-
IPASS_ENABLE_TRANSFER
-
If 1 enables the forwarding of iPass cable present signal to MB CPLD
- using ctrlport requests. On change from 0 to 1 the current status is
- transferred to the MB CPLD via SPI ctrlport request initially.
This register is defined in HDL source file x4xx_gpio_spi.v.
-
-
-
-
-
-Starts a SPI transaction
-
-
-
-
-
Bits
Name
-
-
-
31..0w
-
-
SPI_DATA (initialvalue=0)
-
Payload to be sent for the SPI transaction. If the payload is shorter than 32 bits,
- it must be aligned to the MSbs in this field. LSbs are ignored in this scenario.
This register is defined in HDL source file x4xx_gpio_spi.v.
-
-
-
-
-
-Contains information pertaining this SPI controller block.
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..8
-
-
Reserved
-
-
-
-
-
-
-
7..4
-
-
Reserved
-
-
-
-
-
-
-
3..0
-
-
SLAVE_COUNT
-
Indicates the number SPI slaves configurable by the controller.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DIO_REGMAP
-
-
DIO_REGS
- Registers to control the GPIO buffer direction on the FPGA connected to
- the DIO board. Further registers enable different sources to control and
- read the GPIO lines as master. The following diagram shows how source
- selection multiplexers are arranged, as well as an indicator for the
- register that control them.
-
- Make sure the GPIO lines between FPGA and GPIO board are not driven by
- two drivers. Set the DIO registers in PS_CPLD_BASE_REGMAP appropriately.
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Sets whether the DIO signal line is driven by this register interface
- or the user application.
- 0 = user application is master, 1 = output of SW_DIO_CONTROL is master
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Set the direction of FPGA buffer connected to DIO ports on the DIO board.
- Each bit represents one signal line. 0 = line is an input to the FPGA,
- 1 = line is an output driven by the FPGA.
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Controls the values on each DIO signal line in case the line master is
- set to PS in DIO_MASTER_REGISTER.
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Controls whether the DIO lines reflect the state of DIO_MASTER_REGISTER
- or the radio blocks. 0 = DIO_MASTER_REGISTER,
- 1 = Radio block output(DIO_OVERRIDE)
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Controls which radio block to use the ATR state from to determine the
- state of the DIO lines.
- 0 = Radio#0
- 1 = Radio#1
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Controls which of the two available digital interfaces controls the DIO lines.
- 0 = Digital interface from Radio#0,
- 1 = Digital Interface from Radio#1.
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Controls whether the radio input to the DIO_SOURCE_REGISTER mux
- connects to the ATR control or a Digital interface block. The output
- of the mux controlled by this bit goes to DIO_SOURCE_REGISTER.
- 0 = Drive the ATR state(RADIO_SOURCE_REGISTER), 1 = Drive
- Digital interface block(Output of INTERFACE_DIO_SELECT).
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Controls which source is forwarded to the DIO_MASTER_REGISTER mux.
- This configuration is applied independently for each DIO line.
- 0 = MPM Ctrlport endpoint, 1 = PS Netlist DIO signal.
-
-
-
-
-
Bits
Name
-
-
-
31..28
-
-
Reserved
-
-
-
-
-
-
-
27..16
-
-
DIO_PORT_B (initialvalue=0)
-
-
-
-
-
-
-
15..12
-
-
Reserved
-
-
-
-
-
-
-
11..0
-
-
DIO_PORT_A (initialvalue=0)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DMA_REGMAP
-
-
-
XILINX_DMA_REGISTERS
-
-
Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11
- This is the map that the nixge driver uses in Ethernet DMA to
- move data between the Processing System's architecture and the fabric.
- This map is a combination of two main components: a Xilix AXI DMA engine
- and some registers for MAC/PHY control.
-
This window is defined in HDL source file common_regs.v.
-
-
-
-
-
-Refer to Xilinx' AXI DMA v7.1 IP product guide for further
- information on this register map:
- https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
-
-
This register is defined in HDL source file x4xx_global_regs.v.
-
-
-
-
-
-Control register for clocking resources.
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
PPS_BRC_DELAY
-
Number of base reference clock cycles from appearance of the PPS
- rising edge to the occurrence of the aligned edge of base reference
- clock and PLL reference clock at the sample PLL output. This number
- is the sum of the actual value based on PLL_SYNC_DELAY (also
- accumulate the fixed amount of clock cycles) and if any the number of
- cycles the SPLL requires from issuing of the SYNC signal to the
- aligned edge (with LMK04832 = 0).
- The number written to this register has to be reduced by 1 due to
- HDL implementation.
-
-
-
-
-
-
23..16
-
-
PLL_SYNC_DELAY
-
Due to the HDL implementation the rising edge of the SYNC signal for
- the LMK04832 is generated 2 clock cycles after the PPS rising edge.
- This delay can be further increased by setting this delay value
- (e.g. PLL_SYNC_DELAY=3 will result in a total delay of 5 clock cycles).
- In case two X400 devices are connected using the PPS and reference clock the master delay value needs to be 3 clock cycles
- higher than the slave delay value to align the LMK sync edges in time.
Assertion triggers the SYNC signal generation for LMK04832 after the next appearance of the PPS rising edge.
- There is no self reset on this trigger.
- Keep this trigger asserted until PLL_SYNC_DONE is asserted.
-
-
-
-
-
-
7..6
-
-
Reserved
-
-
-
-
-
-
-
5..4
-
-
TRIGGER_IO_SELECT (initialvalue=TRIG_IO_INPUT)
-
IMPORTANT! SW must ensure any TRIG_IO consumers (downstream devices) ignore
- and/or re-sync after enabling this port, since the output-enable is basically
- asynchronous to the actual TRIG_IO driver.
-
-
- The values for this bitfield are in the TRIG_IO_ENUM table.
- (show here)
-
-
-
-
-
-
-
-
-
-
Value
-
Name
-
-
-
-
-
-
0
-
-
-
TRIG_IO_INPUT
-
-
-
-
-
-
-
-
1
-
-
-
TRIG_IO_PPS_OUTPUT
-
-
-
-
-
-
-
-
- This enumerated type is defined in HDL source file x4xx_global_regs.v.
-
-
-
-
-
-
-
-
-
-
-
3r
-
-
REFCLK_LOCKED
-
RESERVED. This bit is not implemented on X4xx and reads as 0.
-
-
-
-
-
-
2
-
-
REF_SELECT
-
RESERVED. This bit is not implemented on X4xx and reads as 0.
-
-
-
-
-
-
1..0
-
-
PPS_SELECT (initialvalue=PPS_INT_25MHZ)
-
Select the source of the PPS signal.
- For the internal generation the value depending on the base reference clock has to be chosen.
- The external reference is taken from the PPS_IN pin and is independent of the base reference clock.
-
-
- The values for this bitfield are in the PPS_ENUM table.
- (show here)
-
-
-
-
-
-
-
-
-
-
Value
-
Name
-
-
-
-
-
-
0
-
-
-
PPS_INT_25MHZ
-
-
-
-
-
-
-
-
1
-
-
-
PPS_INT_10MHZ
-
-
-
-
-
-
-
-
2
-
-
-
PPS_EXT
-
-
-
-
-
-
-
-
- This enumerated type is defined in HDL source file x4xx_global_regs.v.
-
This register is defined in HDL source file x4xx_global_regs.v.
-
-
-
-
-
-Control registers for PPS generation.
-
-
-
-
-
Bits
Name
-
-
-
31
-
-
PPS_RC_ENABLED
-
Enables the PPS signal in radio clock domain. Please make sure that
- the values of PPS_BRC_DELAY, PPS_PRC_DELAY, PRC_RC0_DIVIDER and
- PRC_RC1_DIVIDER are set before enabling this bit. It is recommended
- to disable the PPS for changes on the other values. Use a wait time of
- at least 1 second before changing this value to ensure the values are
- stable for the next PPS edge.
-
-
-
-
-
-
30..26
-
-
Reserved
-
-
-
-
-
-
-
25..0
-
-
PPS_PRC_DELAY
-
The number of PLL reference clock cycles from one aligned edge to the
- desired aligned edge to issue the PPS in radio clock domain. This
- delay is configurable to any aligned edge within a maximum delay of 1
- second (period of PPS).
- The value written to the register has to be reduced by 5 due to
- HDL implementation.
This register is defined in HDL source file x4xx_global_regs.v.
-
-
-
-
-
-Build seed used for this compilation. Making this value readable
- ensures that compilation results are affected by the value in this
- register.
-
-
This register is defined in HDL source file x4xx_global_regs.v.
-
-
-
-
-
-Control registers for PPS clock crossing to the radio clock domain.
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..21
-
-
Reserved
-
-
-
-
-
-
-
20..16
-
-
PRC_RC1_DIVIDER
-
Clock multiplier used to generate radio clock 1 from PLL reference clock.
- The value written to the register has to follow the following formula:
- PRC_RC1_DIVIDER = (RADIO_CLK_1 / PRC_CLK) * 2 - 2
-
-
-
-
-
-
15..8
-
-
Reserved
-
-
-
-
-
-
-
7..5
-
-
Reserved
-
-
-
-
-
-
-
4..0
-
-
PRC_RC0_DIVIDER
-
Clock multiplier used to generate radio clock 0 from PLL reference clock.
- The value written to the register has to follow the following formula:
- PRC_RC0_DIVIDER = (RADIO_CLK_0 / PRC_CLK) * 2 - 2
This register is defined in HDL source file x4xx_global_regs.v.
-
-
-
-
-
-Status register for mfg_test functions.
-
-
-
-
-
Bits
Name
-
-
-
31..26
-
-
Reserved
-
-
-
-
-
-
-
25..0
-
-
MFG_TEST_FPGA_AUX_REF_FREQ
-
Report the time between rising edges on the FPGA_REF_CLK
- input port in 40 MHz Clock ticks. If the count extends
- to 1.2 seconds without an edge, the value reported is set
- to zero.
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x00C000 + i*4
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file x4xx_gpio_atr.v.
-It uses RegType GPIO_ATR_STATE which is defined in HDL source file x4xx_gpio_atr.v.
-
-
-
-
-
-Holds a single bit setting for GPIO lines in both ports for a particular ATR sate
-Describes GPIO behavior for the different ATR states. When ATR_OPTION
- is set to use the DB states, TX and RX states for RF0 and RF1 are
- combined to create a single vector. This creates 16 different
- combinations, each with its own register. When ATR_OPTION is set to
- classic ATR, offsets 0x00-0x03 in this register group will be driven
- in accordance with the state of RF0, and offsets 0x04-0x07 will be
- driven in accordance with the state of RF1.
- CLASSIC ATR MAPPING: Idle[RF0:0x00; RF1:0x04], RX[RF0:0x01; RF1:0x05],
- TX[RF0:0x02; RF1:0x06], FDX[RF0:0x03; RF1:0x07]
-
-
This register is defined in HDL source file x4xx_gpio_atr.v.
-
-
-
-
-
-Controls the RF state mapping of each GPIO line when classic
- ATR mode is active.
-
-
-
-
-
Bits
Name
-
-
-
31..28
-
-
Reserved
-
-
-
-
-
-
-
27..16
-
-
RF_SELECT_B (initialvalue=0)
-
Set which RF channel's state to reflect in the pins of
- HDMI connector B when ATR_OPTION is set to classic ATR.
- Controlled in a per-pin basis.
- 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03)
- 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)
-
-
-
-
-
-
15..12
-
-
Reserved
-
-
-
-
-
-
-
11..0
-
-
RF_SELECT_A (initialvalue=0)
-
Set which RF channel's state to reflect in the pins for
- HDMI connector A when ATR_OPTION is set to classic ATR.
- Controlled in a per-pin basis.
- 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03)
- 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)
This register is defined in HDL source file x4xx_gpio_atr.v.
-
-
-
-
-
-Controls whether GPIO lines use the TX and RX state of an RF channel
- (Classic ATR) or the daughterboard state the selector for the
- ATR_STATE.
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..8
-
-
Reserved
-
-
-
-
-
-
-
7..1
-
-
Reserved
-
-
-
-
-
-
-
0
-
-
ATR_OPTION (initialvalue=0)
-
Sets the scheme in which RF states in the radio will control GPIO
- lines. 0 = DB state is used. RF states are combined and the
- GPIO state is driven based on all 16 ATR_STATE registers.
- 1 = Each RF channel has its separate ATR state(Classic ATR).
- Use register CLASSIC_ATR_CONFIG to indicate the RF channel
- to which each GPIO line responds to.
This register is defined in HDL source file ctrlport_to_jtag.v.
-
-
-
-
-
-
-
Received data (TDO)
-
-
-
-
-
-
-
-
-
-
-
-
MB_CPLD_PL_REGMAP
-
-
This register map is available using the PL CPLD SPI interface.
-All protocol masters controller by this register map are running with a clock frequency of 50 MHz.
This register is defined in HDL source file uhd_regs.v.
-
-
-
-
-
-
-
Definition of this register depends on Protocol
-
10GBE
-
READ - Status
-
-
0 = status_crc_error
-
1 = status_fragment_error
-
2 = status_txdfifo_ovflow
-
3 = status_txdfifo_udflow
-
4 = status_rxdfifo_ovflow
-
5 = status_rxdfifo_udflow
-
6 = status_pause_frame_rx
-
7 = status_local_fault
-
8 = status_remote_fault
-
-
WRITE - Ctl
-
-
0 = ctrl_tx_enable
-
-
100 GBE
-
READ - Status
-
-
0 = tx_ovfout - Sets if TX overflow reported by CMAC
- (Stays set till MAC is reset). This is a fatal error
-
1 = tx_unfout - Sets if TX underflow reported by CMAC
- (Stays set till MAC is reset). This is a fatal error
-
2 = stat_rx_aligned - goes high when CMAC has finished
- alignment, and is ready to start reception of traffic.
-
3 = mac_dropped_packet - If the mac RX wants to push data(TVALID)
- but upstream is trying to hold(TREADY)off we drop a packet.
- Upstream circuitry should detect this when traffic is forked
- between CHDR and CPU, so this bit will only set if there is a
- HW design error.
-
4 = auto_config_done - This bit goes high when the auto_config
- state machine finishes operation. It is very similiar to
- stat_rx_alligned, but waits for extra writes which occur
- after allignement to complete.
-
24:16 = pause_mask - readable version of pause_mask bellow.
-
-
WRITE - Ctl
-
-
0 = auto_enable - Defaults to ON after reset - Enables a
- state machine that performs CMAC register writes to
- bring up the MAC without SW intervention.
-
24:16 = pause_mask - A second layer of enables(the first being
- register in the CMAC) on the pause_request mechanic. Bits
- 7:0 of enable pause on PFC7:0. Bit 8 enables global pause
- request (not priority controlled). The mask is used for TX
- and RX.
This register is defined in HDL source file pl_cpld_regs.v.
-
-
-
-
-
-Provides to the LEDs of the QSFP ports.
- Write access will directly change the LED status.
- The LED lights up if the corresponding bit is set.
-
-
This register is defined in HDL source file pl_cpld_regs.v.
-
-
-
-
-
-This register returns (in YYMMDDHH format) the oldest revision
- that is still compatible with this one. Compatible means that
- registers or register bits may have been added, but not
- modified or deleted (see OLDEST_CPLD_REVISION of CONSTANTS_REGMAP).
-
-
This register is defined in HDL source file pl_cpld_regs.v.
-
-
-
-
-
-Git hash of commit used to build this image.
- Value equals 0xDEADBEEF if the git hash was not used during synthesis.
-
-
-
-
-
Bits
Name
-
-
-
31..28
-
-
GIT_CLEAN
-
0x0 in case the git status was clean
- 0xF in case there were uncommitted changes
-
-
-
-
-
-
27..0
-
-
GIT_HASH
-
7 hex digit hash code of the commit
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PL_CPLD_REGMAP
- This register map is available from the PS via AXI and MPM endpoint.
- Its size is 128K (17 bits). Only the 17 LSBs are used as address in this documentation.
-
This window is defined in HDL source file cpld_interface.v.
-
-
-
-
-
-All registers of the second DB CPLD. Register map will be added later on.
-
-
-
-
-
-
-
-
-
-
-
-
PL_DMA_MASTER_REGMAP
- This is a regmap to document the different ports that have access to the PS system memory.
- Each port may have different restrictions on system memory. See the corresponding window
- for details
-
This window is defined in HDL source file common_regs.v.
-
-
-
-
-
-The HPC0 port of the PS is used for general purpose cache-coherent accesses
- to the PS system memory. Different applications may use it for different
- purposes. Its access is configured as follows:
-
This window is defined in HDL source file common_regs.v.
-
-
-
-
-
-The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave
- interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx.
- Its access is configured as follows:
-
-
Offset
Size
Description
-
0x000800000000
0x000800000000
DDR_HIGH
-
0x00000000
0x80000000
DDR_LOW
-
0xC0000000
0x20000000
QSPI
-
-
-
-
-
-
-
-
-
-
-
-
-
PS_CPLD_BASE_REGMAP
-
-
DIO_REGS
- Registers to control the GPIO buffer direction on the DIO board connected to the FPGA.
- Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers.
- Set the direction in the FPGA's DIO register appropriately.
-
This register is defined in HDL source file ps_cpld_regs.v.
-
-
-
-
-
-Set the direction of FPGA buffer connected to DIO ports on the DIO board.
- Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA.
-
-
This register is defined in HDL source file ps_cpld_regs.v.
-
-
-
-
-
-Register to control the PL part DB SPI connection and reset generation.
- The DB connection is clocked with PLL reference clock. Ensure this clock is stable
- and enabled before starting any SPI request.
- The PLL reference clock can be disabled if both DB connections are disabled or inactive.
- To enable the DB connection, enable clock with one write access and release
- reset with the next write access.
- To disable the DB connection, assert reset with one write access and
- disable clocks with the next write access.
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..22
-
-
Reserved
-
-
-
-
-
-
-
21w
-
-
ASSERT_RESET_DB1
-
Writing with this flag set asserts reset for DB 1 (overrides RELEASE_RESET_DB1)
-
-
-
-
-
-
20w
-
-
ASSERT_RESET_DB0
-
Writing with this flag set asserts reset for DB 0 (overrides RELEASE_RESET_DB0)
-
-
-
-
-
-
19..18
-
-
Reserved
-
-
-
-
-
-
-
17w
-
-
RELEASE_RESET_DB1
-
Writing with this flag set releases DB 1 reset. (may be overwritten by ASSERT_RESET_DB1)
-
-
-
-
-
-
16w
-
-
RELEASE_RESET_DB0
-
Writing with this flag set releases DB 0 reset. (may be overwritten by ASSERT_RESET_DB0)
-
-
-
-
-
-
15
-
-
Reserved
-
-
-
-
-
-
-
14w
-
-
DISABLE_PLL_REF_CLOCK
-
Writing with this flag set disables the PLL reference clock (overrides ENABLE_PLL_REF_CLOCK). Assert this flag to reconfigure the clock.
-
-
-
-
-
-
13w
-
-
DISABLE_CLOCK_DB1
-
Writing with this flag set disables DB 1 clock forwarding (overrides ENABLE_CLOCK_DB1)
-
-
-
-
-
-
12w
-
-
DISABLE_CLOCK_DB0
-
Writing with this flag set disables DB 0 clock forwarding (overrides ENABLE_CLOCK_DB0)
-
-
-
-
-
-
11
-
-
Reserved
-
-
-
-
-
-
-
10w
-
-
ENABLE_PLL_REF_CLOCK
-
Writing with this flag set enables the PLL reference clock. Assert this flag after PLL reference clock is stable. (may be overwritten by DISABLE_PLL_REF_CLOCK)
-
-
-
-
-
-
9w
-
-
ENABLE_CLOCK_DB1
-
Writing with this flag set enables DB 1 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB1)
-
-
-
-
-
-
8w
-
-
ENABLE_CLOCK_DB0
-
Writing with this flag set enables DB 0 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB0)
-
-
-
-
-
-
7..6
-
-
Reserved
-
-
-
-
-
-
-
5r
-
-
DB1_RESET_ASSERTED
-
Indicates that reset is asserted for DB 1.
-
-
-
-
-
-
4r
-
-
DB0_RESET_ASSERTED
-
Indicates that reset is asserted for DB 0.
-
-
-
-
-
-
3
-
-
Reserved
-
-
-
-
-
-
-
2r
-
-
PLL_REF_CLOCK_ENABLED
-
Indicates if the PLL reference clock for the PL interface is enabled.
-
-
-
-
-
-
1r
-
-
DB1_CLOCK_ENABLED
-
Indicates if a clock is forwarded to DB 1.
-
-
-
-
-
-
0r
-
-
DB0_CLOCK_ENABLED
-
Indicates if a clock is forwarded to DB 0.
-
-
-
-
-
-
-
-
-
-
-
PS_CPLD_BASE_REGS
- Basic registers containing version and capabilites information.
-
This register is defined in HDL source file ps_cpld_regs.v.
-
-
-
-
-
-This register returns (in YYMMDDHH format) the oldest revision
- that is still compatible with this one. Compatible means that
- registers or register bits may have been added, but not
- modified or deleted (see OLDEST_CPLD_REVISION of CONSTANTS_REGMAP).
-
-
This register is defined in HDL source file ps_power_regs.v.
-
-
-
-
-
-Controls the power supplies for the iPass connectors.
-
-
-
-
-
Bits
Name
-
-
-
31r
-
-
IPASS_POWER_FAULT1
-
Asserted signal indicates a power fault in power switch for iPass
- connector 1. Sticky bit. Asserted on occurrence. Reset using
- IPASS_CLEAR_POWER_FAULT1.
Asserted signal indicates a power fault in power switch for iPass
- connector 0. Sticky bit. Asserted on occurrence. Reset using
- IPASS_CLEAR_POWER_FAULT0.
This window is defined in HDL source file uhd_regs.v.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RADIO_CTRLPORT_REGMAP
-
-
RADIO_CTRLPORT_WINDOWS
- Each radio's CtrlPort peripheral interface is divided into the
- following memory spaces. Note that the CtrlPort peripheral interface
- starts at offset 0x80000 in the RFNoC Radio block's register space.
- The following diagram displays the distribution of the CtrlPort
- interface to the different modules it interacts with.
-
-
-
-
This window is defined in HDL source file x4xx_core_common.v.
-
-
-
-
-
-Register space reserved for configuring a digital interface over the GPIO lines.
- Currently, SPI is the only supported protocol.
-
-
-
-
-
-
-
-
-
-
-
-
RECONFIG_REGMAP
-
-
RECONFIG_REGS
- These registers are used to upload and verify a new primary image to the
- Max 10 FPGA on-chip flash when configured to support dual configuration
- images. The steps below outline the process of verifying/preparing the
- new image to be written, erasing the current image, writing the new
- image, and verifying the new image was successfully written.
-
Prepare the data...
-
The Max 10 FPGA build should generate a *cfm0_auto.rpd
- file The *.rpd file is a "raw programming
- data" file holding all data related to the
- configuration image (CFM0). There are two
- important items to note regarding the addresses.
- First the *rpd data uses byte addresses.
- Second, the start/end addresses defined by
- FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses
-
As a sanity check, verify the size of the raw
- programming data for CFM0 correspond to the address
- range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by
- reading the values from FLASH_CFM0_START_ADDR_REG and
- FLASH_CFM0_END_ADDR, subtract both values, add one and
- multiply by four.
-
-
Having passed the sanity check the *.rpd data must
- now be manipulated into the form required by Altera's
- on-chip flash IP. Two operations must be performed.
- First the data must be converted from bytes to 32-bit
- words. Second the bit order must be reversed. This is
- illustrated in in the following table which shows byte
- address and data from the *.rpd file compared to the
- word address and data to be written to the on-chip
- flash.
-
-
.Map Addr
.Map Data
Flash Addr
Flash Data
-
0x2B800
0x01
0xAC00
0x8040C020
-
0x2B801
0x02
-
0x2B802
0x03
-
0x2B803
0x04
-
0x2B804
0x05
0xAC01
0xA060E010
-
0x2B805
0x06
-
0x2B806
0x07
-
0x2B807
0x08
-
-
-
The resulting set of flash address data pairs should
- be used when writing FLASH_ADDR_REG and
- FLASH_WRITE_DATA_REG to update the CFM0 image.
- However, prior to writing the new image the old image
- must be erased.
-
-
-
-
Erase the current primary flash image...
-
Read FLASH_STATUS_REG and verify no error bits are
- asserted and that all read, write, and erase operations
- are idle.
-
Disable write protection of the flash by strobing the
- FLASH_DISABLE_WP_STB bit of FLASH_CONTROL_REG.
-
-
Verify write protection is disabled and no errors are
- present by reading FLASH_STATUS_REG.
-
Initiate the erase operation by setting
- FLASH_ERASE_SECTOR and strobing FLASH_ERASE_STB of
- FLASH_CONTROL_REG.
-
Poll the FLASH_ERASE_IDLE bit of
- FLASH_STATUS_REG until it de-asserts indicating the
- erase operation is complete, then verify the operation
- was successful by checking that the FLASH_ERASE_ERR
- bit is de-asserted. Erase operations are expected to
- take a maximum of 350 msec. Upon completion of the erase
- operation write protection will remain disabled.
-
-
Erase additional sectors as required (see
- FLASH_ERASE_SECTOR for details) by restarting with first
- step.
-
-
-
Write the new primary flash image...
-
Read FLASH_STATUS_REG and verify no error bits are
- asserted, all read, write, and erase operations are
- idle, and write protection is disabled.
-
Set the target address for the write to the Max 10
- on-chip flash by writing value from
- FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.
-
Set the data to be written to this address by writing
- the new 32-bit word of the new image to
- FLASH_WRITE_DATA_REG.
-
Initiate the write by strobing FLASH_WRITE_STB of
- FLASH_CONTROL_REG.
-
Poll the FLASH_WRITE_IDLE bit of
- FLASH_STATUS_REG until it de-asserts indicating the
- write operation is complete, then verify the operation
- was successful by checking that the FLASH_WRITE_ERR
- bit is de-asserted. Write operations are expected to
- take a maximum of 550 usec.
-
Upon completion of the write operation return to step
- 2, incrementing the target address by one, and writing
- the next 32-bit word to Max10FlashWriteDatReg. If this
- was the last write, indicated by writing to
- FLASH_PRIMARY_IMAGE_END_ADDR, proceed to the next step
- to enable write protection.
-
After writing the new image enable write protection
- by strobing the FLASH_ENABLE_WP_STB bit of
- FLASH_CONTROL_REG.
-
-
-
Verify the new primary flash image...
-
Read FLASH_STATUS_REG and verify no error bits are
- asserted and that all read, write, and erase operations
- are idle.
-
Set the target address for the read in the Max 10
- on-chip flash by writing value from
- FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.
-
Initiate the read by strobing FLASH_READ_STB of
- FLASH_CONTROL_REG.
-
Poll the FLASH_READ_IDLE bit of
- FLASH_STATUS_REG until it de-asserts indicating the
- read operation is complete, then verify the operation
- was successful by checking that the FLASH_READ_ERR
- bit is de-asserted. There is no guidance on exactly how
- long reads take to complete, but they are expected to be
- fairly quick. A very conservative timeout on this
- polling would be similar to that used for write
- operations.
-
Upon completion of the read operation the resulting
- data returned by the on-chip flash will be available in
- Max10FlashReadDatReg. Read this register, compare to
- expected value previously written, and ensure they
- match.
-
Return to step 2, incrementing the target
- address by one. If this was the last read verification
- is complete and no further action is required.
-
-
-
After the flash has been erased, programmed, and verified, a power
- cycle is required for the new image to become active.
-
-
-
-
-
FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration
-These values are the start and end address of the CFM image flash
- sector from Intel's On-Chip Flash IP Generator.
- Be aware that three different values exist per each of the two
- supported MAX10 variants: 10M04 and 10M08
- Note that the values given in the IP generator are byte based where
- the values of this enum are U32 based (divided by 4).
-
-
-
-
Value
-
Name
-
-
-
-
-
-
Dec
-
-
Hex
-
-
-
-
-
-
4096
-
-
0x01000
-
-
-
FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04
-
-
-
-
-
-
-
-
8192
-
-
0x02000
-
-
-
FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08
-
-
-
-
-
-
-
-
39936
-
-
0x09C00
-
-
-
FLASH_PRIMARY_IMAGE_START_ADDR_10M04
-
-
-
-
-
-
-
-
44032
-
-
0x0AC00
-
-
-
FLASH_PRIMARY_IMAGE_START_ADDR_10M08
-
-
-
-
-
-
-
-
75775
-
-
0x127FF
-
-
-
FLASH_PRIMARY_IMAGE_END_ADDR_10M04
-
-
-
-
-
-
-
-
79871
-
-
0x137FF
-
-
-
FLASH_PRIMARY_IMAGE_END_ADDR_10M08
-
-
-
-
-
-
-
-
- This enumerated type is defined in HDL source file reconfig_engine.v.
-
This register is defined in HDL source file reconfig_engine.v.
-
-
-
-
-
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..17
-
-
Reserved
-
-
-
-
-
-
-
16
-
-
FLASH_MEM_INIT_ENABLED
-
This bit is asserted when the flash can hold an image with memory
- initialization.
-
-
-
-
-
-
15..14
-
-
Reserved
-
-
-
-
-
-
-
13
-
-
FLASH_WRITE_ERR
-
This bit is asserted when write operation fails. Clear this error
- by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In
- the event of a write error...
-
the primary configuration image may be corrupted, and
- power cycling the board may result unknown behavior.
-
write protection of the flash will automatically be
- re-enabled.
-
attempts to disable write protection will be ignored.
-
attempts to read/write/erase the flash will be ignored.
-
-
-
-
-
-
12
-
-
FLASH_WRITE_IDLE
-
This bit is de-asserted when a write operation is in progress. Poll
- this bit after strobing the FLASH_WRITE_STB bit of
- FLASH_CONTROL_REG to determine when the write operation has
- completed, then check the FLASH_WRITE_ERR bit to verify the
- operation was successful.
-
-
-
-
-
-
11..10
-
-
Reserved
-
-
-
-
-
-
-
9
-
-
FLASH_ERASE_ERR
-
This bit is asserted when an erase operation fails. Clear this
- error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In
- the event of an erase error...
-
the primary configuration image may be corrupted, and
- power cycling the board may result in unknown behavior.
-
write protection of the flash will automatically be
- re-enabled.
-
attempts to disable write protection will be ignored.
-
attempts to read/write/erase the flash will be ignored.
-
-
-
-
-
-
8
-
-
FLASH_ERASE_IDLE
-
This bit is de-asserted when an erase operation is in progress. Poll
- this bit after strobing the FLASH_ERASE_STB bit of
- FLASH_CONTROL_REG to determine when the erase operation has
- completed, then check the FLASH_ERASE_ERR bit to verify the
- operation was successful.
-
-
-
-
-
-
7..6
-
-
Reserved
-
-
-
-
-
-
-
5
-
-
FLASH_READ_ERR
-
This bit is asserted when a read operation fails. Clear this error
- by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the
- event of a read error...
-
the data in FLASH_READ_DATA_REG is invalid.
-
attempts to disable write protection will be ignored.
-
attempts to read/write/erase the flash will be ignored.
-
-
-
-
-
-
4
-
-
FLASH_READ_IDLE
-
This bit is de-asserted when a read operation is in progress. Poll
- this bit after strobing the FLASH_READ_STB bit of
- FLASH_CONTROL_REG to determine when the read operation has
- completed, then check the FLASH_READ_ERR bit to verify the
- operation was successful.
-
-
-
-
-
-
3..1
-
-
Reserved
-
-
-
-
-
-
-
0
-
-
FLASH_WP_ENABLED
-
This bit is asserted when the flash is write protected and
- de-asserted when write protection is disabled.
-
Write protection must be enabled prior to performing read
- operations.
-
Write protection must be disabled prior to performing write and
- erase operations.
This register is defined in HDL source file reconfig_engine.v.
-
-
-
-
-
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..11
-
-
Reserved
-
-
-
-
-
-
-
10w
-
-
CLEAR_FLASH_ERASE_ERROR_STB (Strobe)
-
Strobe this bit to clear an erase error.
-
-
-
-
-
-
9w
-
-
CLEAR_FLASH_WRITE_ERROR_STB (Strobe)
-
Strobe this bit to clear a write error.
-
-
-
-
-
-
8w
-
-
CLEAR_FLASH_READ_ERROR_STB (Strobe)
-
Strobe this bit to clear a read error.
-
-
-
-
-
-
7..5w
-
-
FLASH_ERASE_SECTOR (Strobe)
-
Defines the sector to be erased. Has to be set latest with the
- write access which starts the erase operation by strobing
- FLASH_ERASE_STB.
- With 10M04 variants, if the flash is configured to support memory
- initialization (see FLASH_MEM_INIT_ENABLED flag) the sectors 2
- to 4 have to be erased. If the flag is not asserted only sector 4
- has to be erased.
- With 10M08 variants, the sectors to be erased are 3 to 5 when
- using memory initialization or only sector 5 otherwise.
-
-
-
-
-
-
4w
-
-
FLASH_ERASE_STB (Strobe)
-
Strobe this bit to erase the primary Max10 configuration image
- (CFM0).
-
Prior to strobing this bit verify no other write or erase
- operations are in progress, write protection is disabled, and no
- error bits are asserted by reading FLASH_STATUS_REG.
-
Attempts to erase the primary image while other write or erase
- operations are in progress will be ignored.
-
Attempts to erase the primary image when write protection is
- enabled will be ignored.
-
Strobing this bit and FLASH_WRITE_STB simultaneously will
- result both the erase and the write operation being ignored, both
- corresponding error bits being set, and write protection being
- re-enabled.
-
After strobing this bit poll the FLASH_ERASE_IDLE and
- FLASH_ERASE_ERR bits of FLASH_STATUS_REG to determine when
- the erase operation is complete and if it was successful.
-
-
-
-
-
-
3w
-
-
FLASH_WRITE_STB (Strobe)
-
Strobe this bit to write the data contained in
- FLASH_WRITE_DATA_REG to the flash address identified in
- FLASH_ADDR_REG.
-
The flash must be erased before writing new data.
-
Prior to strobing this bit verify write protection is
- disabled, no other write or erase operations are in progress, and
- no error bits are asserted by reading FLASH_STATUS_REG.
-
Attempts to write data while other write or erase operations
- are in progress will be ignored.
-
Attempts to write data with write protection enabled will be
- ignored.
-
Strobing this bit and FLASH_ERASE_STB simultaneously will
- result in both the write and erase operation being ignored,
- both corresponding error bits being set, and write protection
- being re-enabled.
-
After strobing this bit poll theMax10FlashWriteIdle and
- FLASH_WRITE_ERR bits of FLASH_STATUS_REG to determine when
- the write operation is complete and if it was successful.
-
-
-
-
-
-
2w
-
-
FLASH_READ_STB (Strobe)
-
Strobe this bit to read data from the flash address identified in
- FLASH_ADDR_REG.
-
Prior to strobing this bit verify no read, write, or erase
- operations are in progress, no error bits are asserted, and
- write protection is enabled by reading FLASH_STATUS_REG.
-
Attempts to read data while other operations are in progress
- or while write protection is disabled will be ignored.
-
After strobing this bit poll the FLASH_READ_IDLE and
- FLASH_READ_ERR bits of FLASH_STATUS_REG to determine when
- the read operation is complete and if it was successful.
-
Upon successful completion the data read from flash will be
- available in FLASH_READ_DATA_REG.
-
-
-
-
-
-
1w
-
-
FLASH_DISABLE_WP_STB (Strobe)
-
Strobe this bit to disable write protection to the section of the
- Max 10 on-chip flash storing the primary configuration image
- (CFM0).
-
Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to
- determine the current state of write protection.
-
Prior to strobing this bit verify no read operations are in
- progress and no error bits are asserted by reading
- FLASH_STATUS_REG.
-
Attempts to disable write protection while a read is in
- progress will be ignored.
-
Attempts to disable write protection will be ignored if
- this bit is strobed simultaneously with either FLASH_READ_STB
- or FLASH_ENABLE_WP_STB.
-
Write protection must be disabled prior to performing erase or
- write operations.
-
Upon completion of erase/write operations write protection
- will remain disabled. When not actively erasing or writing a new
- image write protection should be enabled to avoid data
- corruption.
-
-
-
-
-
-
0w
-
-
FLASH_ENABLE_WP_STB (Strobe)
-
Strobe this bit to enable write protection to the section of the
- Max 10 on-chip flash storing the primary configuration image
- (CFM0).
-
Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to
- determine the current state of write protection.
-
Prior to strobing this bit verify no write or erase operations
- are in progress and no error bits are asserted by reading
- FLASH_STATUS_REG.
-
Attempts to enable write protection while erase or write
- operations are in progress will be ignored.
-
Write protection must be enabled prior to performing
- read operations.
-
Write protection should be enabled after completing
- write or erase operations to prevent data corruption.
This register is defined in HDL source file reconfig_engine.v.
-
-
-
-
-
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..17
-
-
Reserved
-
-
-
-
-
-
-
16..0
-
-
FLASH_ADDR
-
This field holds the target address for the next read or
- write operation. Set this field prior to strobing the
- FLASH_WRITE_STB and FLASH_READ_STB bits of
- FLASH_CONTROL_REG. Valid addresses are defined by the
- FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration.
This window is defined in HDL source file x410_rfdc_regs.v.
-
-
-
-
-
-Register space for controlling the data clock MMCM instance
- within the RFDC block design.
- Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the
- regiter space description in chapter 2.
- (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)
-
-
This register is defined in HDL source file x410_rfdc_regs.v.
-It uses RegType RF_RESET_CONTROL_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-Control register for the RF reset controller.
- Verify the FSM ID before polling starting any reset sequence.
- To use the SW reset triggers: Wait until DB*_DONE is de-asserted.
- Assert either the *_RESET or *_ENABLE bitfields.
- Wait until DB*_DONE is asserted to release the trigger.
- The DB*_DONE signal should then de-assert.
- Note: The *_DB1 constants are not used in the HDL, their purpose is
- merely for documentation.
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..10
-
-
Reserved
-
-
-
-
-
-
-
9
-
-
DAC_ENABLE
-
Write a '1' to this bit to trigger the enable sequence for
- the daughterboard 0 DAC chain. Write a '0' once
- db0_dac_seq_done is asserted.
-
-
-
-
-
-
8
-
-
DAC_RESET
-
Write a '1' to this bit to trigger a reset for the
- daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done
- is asserted.
-
-
-
-
-
-
7..6
-
-
Reserved
-
-
-
-
-
-
-
5
-
-
ADC_ENABLE
-
Write a '1' to this bit to trigger the enable sequence for
- the daughterboard 0 ADC chain. Write a '0' once
- db0_adc_seq_done is asserted.
-
-
-
-
-
-
4
-
-
ADC_RESET
-
Write a '1' to this bit to trigger a reset for the
- daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done
- is asserted.
-
-
-
-
-
-
3..1
-
-
Reserved
-
-
-
-
-
-
-
0
-
-
FSM_RESET
-
Write a '1' to this bit to reset the RF reset controller.
- Write a '0' once db0_fsm_reset_done asserts.
This register is defined in HDL source file x410_rfdc_regs.v.
-It uses RegType RF_RESET_STATUS_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-Status register for the RF reset controller.
- Verify the FSM ID before polling starting any reset sequence.
- Refer to RF*_RESET_CONTROL_REG for instructions on how to use
- the status bits in this register.
- Note: The *_DB1 constants are not used in the HDL, their purpose is
- merely for documentation.
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..12
-
-
Reserved
-
-
-
-
-
-
-
11
-
-
DAC_SEQ_DONE
-
This bit asserts ('1') when the DB0 DAC chain reset sequence
- is completed. The bitfield deasserts ('0') after
- deasserting the issued triggered (enable or reset).
-
-
-
-
-
-
10..8
-
-
Reserved
-
-
-
-
-
-
-
7
-
-
ADC_SEQ_DONE
-
This bit asserts ('1') when the DB0 ADC chain reset sequence
- is completed. The bitfield deasserts ('0') after
- deasserting the issued triggered (enable or reset).
-
-
-
-
-
-
6..4
-
-
Reserved
-
-
-
-
-
-
-
3
-
-
FSM_RESET_DONE
-
This bit asserts ('1') when the DB0 RF reset controller FSM
- reset sequence is completed. The bitfield deasserts ('0')
- after deasserting db0_fsm_reset.
This register is defined in HDL source file x410_rfdc_regs.v.
-It uses RegType RF_AXI_STATUS_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-Status register for the RF AXI-Stream interfaces.
- Note: The *_DB1 constants are not used in the HDL, their purpose is
- merely for documentation.
-
-
-
-
-
-
Bits
Name
-
-
-
31..30
-
-
USER_ADC_TREADY_DB1
-
This bitfield is wired to the user's ADC (DB1) AXI-Stream
- TReady handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
29..28
-
-
USER_ADC_TVALID_DB1
-
This bitfield is wired to the user's ADC (DB1) AXI-Stream
- TValid handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
27..26
-
-
RFDC_ADC_I_TVALID_DB1
-
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
- TValid handshake signals (I portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
25..24
-
-
RFDC_ADC_Q_TVALID_DB1
-
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
- TValid handshake signals (Q portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
23..22
-
-
RFDC_ADC_I_TREADY_DB1
-
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
- TReady handshake signals (I portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
21..20
-
-
RFDC_ADC_Q_TREADY_DB1
-
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
- TReady handshake signals (Q portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
19..18
-
-
RFDC_DAC_TVALID_DB1
-
This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
- TValid handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
17..16
-
-
RFDC_DAC_TREADY_DB1
-
This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
- TReady handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
15..14
-
-
USER_ADC_TREADY
-
This bitfield is wired to the user's ADC (DB0) AXI-Stream
- TReady handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
13..12
-
-
USER_ADC_TVALID
-
This bitfield is wired to the user's ADC (DB0) AXI-Stream
- TValid handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
11..10
-
-
RFDC_ADC_I_TVALID
-
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
- TValid handshake signals (I portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
9..8
-
-
RFDC_ADC_Q_TVALID
-
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
- TValid handshake signals (Q portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
7..6
-
-
RFDC_ADC_I_TREADY
-
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
- TReady handshake signals (I portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
5..4
-
-
RFDC_ADC_Q_TREADY
-
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
- TReady handshake signals (Q portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
3..2
-
-
RFDC_DAC_TVALID
-
This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
- TValid handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
1..0
-
-
RFDC_DAC_TREADY
-
This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
- TReady handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
This register is defined in HDL source file x410_rfdc_regs.v.
-It uses RegType FABRIC_DSP_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-This register provides information to the driver on the type
- of DSP that is instantiated in the fabric.
- The X410 platform supports multiple RF daughterboards, each requiring
- a different fabric RF DSP chain that works with specific RFDC settings.
- Each bandwidth DSP chain has a unique identifier (BW in MHz), this
- information is conveyed in this register to let the driver
- configure the RFDC with the proper settings.
- Also, channel count for the DSP module is included.
- Note: The *_DB1 constants are not used in the HDL, their purpose is
- merely for documentation.
-
-
-
This register is defined in HDL source file x410_rfdc_regs.v.
-
-
-
-
-
-This register enables calibration data in the DAC data path for each of the
- four channels. Each of these bits is normally '0'. When written '1', DAC data
- for the corresponding channel will be constantly driven with the contents of
- the CALIBRATION_DATA register.
-
-
This register is defined in HDL source file x410_rfdc_regs.v.
-
-
-
-
-
-This register shows threshold status for the ADCs. Each bit reflects the
- RFDC's real-time ADC status signals, which will assert when the ADC input
- signal exceeds the programmed threshold value. The status will remain
- asserted until cleared by software.
- The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is
- the location of the tile in the converter column and ZZ is either 01 (the
- lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
- See also the Xilinx document PG269.
-
-
This register is defined in HDL source file x410_rfdc_regs.v.
-It uses RegType ADC_TILEMAP_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-This register describes how the ADCs map to the respective tiles. It
- lets us designate an ADC as channel 0, channel 1, etc. depending on
- how those channels are externally connected to the RFSoC.
-
- For every channel, this register stores the tile number and the block
- number of the converter. This can be used to then address the correct
- converter in the various Xilinx interfaces/APIs.
-
-
-
-
-
-
Bits
Name
-
-
-
31..30
-
-
ADC_TILEMAP_DB1_CHAN3_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 3, daughterboard 1.
-
-
-
-
-
-
29..28
-
-
ADC_TILEMAP_DB1_CHAN3_TILE (initialvalue=0)
-
Tile number of the ADC for channel 3, daughterboard 1.
-
-
-
-
-
-
27..26
-
-
ADC_TILEMAP_DB1_CHAN2_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 2, daughterboard 1.
-
-
-
-
-
-
25..24
-
-
ADC_TILEMAP_DB1_CHAN2_TILE (initialvalue=0)
-
Tile number of the ADC for channel 2, daughterboard 1.
-
-
-
-
-
-
23..22
-
-
ADC_TILEMAP_DB1_CHAN1_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 1, daughterboard 1.
-
-
-
-
-
-
21..20
-
-
ADC_TILEMAP_DB1_CHAN1_TILE (initialvalue=0)
-
Tile number of the ADC for channel 1, daughterboard 1.
-
-
-
-
-
-
19..18
-
-
ADC_TILEMAP_DB1_CHAN0_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 0, daughterboard 1.
-
-
-
-
-
-
17..16
-
-
ADC_TILEMAP_DB1_CHAN0_TILE (initialvalue=0)
-
Tile number of the ADC for channel 0, daughterboard 1.
-
-
-
-
-
-
15..14
-
-
ADC_TILEMAP_DB0_CHAN3_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 3, daughterboard 0.
-
-
-
-
-
-
13..12
-
-
ADC_TILEMAP_DB0_CHAN3_TILE (initialvalue=0)
-
Tile number of the ADC for channel 3, daughterboard 0.
-
-
-
-
-
-
11..10
-
-
ADC_TILEMAP_DB0_CHAN2_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 2, daughterboard 0.
-
-
-
-
-
-
9..8
-
-
ADC_TILEMAP_DB0_CHAN2_TILE (initialvalue=0)
-
Tile number of the ADC for channel 2, daughterboard 0.
-
-
-
-
-
-
7..6
-
-
ADC_TILEMAP_DB0_CHAN1_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 1, daughterboard 0.
-
-
-
-
-
-
5..4
-
-
ADC_TILEMAP_DB0_CHAN1_TILE (initialvalue=0)
-
Tile number of the ADC for channel 1, daughterboard 0.
-
-
-
-
-
-
3..2
-
-
ADC_TILEMAP_DB0_CHAN0_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 0, daughterboard 0.
-
-
-
-
-
-
1..0
-
-
ADC_TILEMAP_DB0_CHAN0_TILE (initialvalue=0)
-
Tile number of the ADC for channel 0, daughterboard 0.
This register is defined in HDL source file x410_rfdc_regs.v.
-It uses RegType DAC_TILEMAP_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-This register describes how the DACs map to the respective tiles. It
- lets us designate an DAC as channel 0, channel 1, etc. depending on
- how those channels are externally connected to the RFSoC.
-
- For every channel, this register stores the tile number and the block
- number of the converter. This can be used to then address the correct
- converter in the various Xilinx interfaces/APIs.
-
-
-
-
-
-
Bits
Name
-
-
-
31..30
-
-
DAC_TILEMAP_DB1_CHAN3_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 3, daughterboard 1.
-
-
-
-
-
-
29..28
-
-
DAC_TILEMAP_DB1_CHAN3_TILE (initialvalue=0)
-
Tile number of the DAC for channel 3, daughterboard 1.
-
-
-
-
-
-
27..26
-
-
DAC_TILEMAP_DB1_CHAN2_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 2, daughterboard 1.
-
-
-
-
-
-
25..24
-
-
DAC_TILEMAP_DB1_CHAN2_TILE (initialvalue=0)
-
Tile number of the DAC for channel 2, daughterboard 1.
-
-
-
-
-
-
23..22
-
-
DAC_TILEMAP_DB1_CHAN1_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 1, daughterboard 1.
-
-
-
-
-
-
21..20
-
-
DAC_TILEMAP_DB1_CHAN1_TILE (initialvalue=0)
-
Tile number of the DAC for channel 1, daughterboard 1.
-
-
-
-
-
-
19..18
-
-
DAC_TILEMAP_DB1_CHAN0_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 0, daughterboard 1.
-
-
-
-
-
-
17..16
-
-
DAC_TILEMAP_DB1_CHAN0_TILE (initialvalue=0)
-
Tile number of the DAC for channel 0, daughterboard 1.
-
-
-
-
-
-
15..14
-
-
DAC_TILEMAP_DB0_CHAN3_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 3, daughterboard 0.
-
-
-
-
-
-
13..12
-
-
DAC_TILEMAP_DB0_CHAN3_TILE (initialvalue=0)
-
Tile number of the DAC for channel 3, daughterboard 0.
-
-
-
-
-
-
11..10
-
-
DAC_TILEMAP_DB0_CHAN2_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 2, daughterboard 0.
-
-
-
-
-
-
9..8
-
-
DAC_TILEMAP_DB0_CHAN2_TILE (initialvalue=0)
-
Tile number of the DAC for channel 2, daughterboard 0.
-
-
-
-
-
-
7..6
-
-
DAC_TILEMAP_DB0_CHAN1_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 1, daughterboard 0.
-
-
-
-
-
-
5..4
-
-
DAC_TILEMAP_DB0_CHAN1_TILE (initialvalue=0)
-
Tile number of the DAC for channel 1, daughterboard 0.
-
-
-
-
-
-
3..2
-
-
DAC_TILEMAP_DB0_CHAN0_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 0, daughterboard 0.
-
-
-
-
-
-
1..0
-
-
DAC_TILEMAP_DB0_CHAN0_TILE (initialvalue=0)
-
Tile number of the DAC for channel 0, daughterboard 0.
This register is defined in HDL source file x410_rfdc_regs.v.
-It uses RegType RFDC_INFO_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-This register provides information about how the RFDC is connected to
- the rest of the fabric.
- Specifically, between the actual RFDC and the RFNoC infrastructure,
- there may be additional resampling (if the RFDC resampler cannot handle
- all the resampling itself) and it is important to know how wide the
- connection from the RFDC gearbox FIFO to the rest of the design is.
- Note: The *_DB1 constants are not used in the HDL, their purpose is
- merely for documentation.
-
-
-
-
-
-
Bits
Name
-
-
-
31..26
-
-
Reserved
-
-
-
-
-
-
-
25..23
-
-
RFDC_INFO_SPC_TX_DB1 (initialvalue=1)
-
Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 1.
-
-
-
-
-
-
22..20
-
-
RFDC_INFO_SPC_RX_DB1 (initialvalue=1)
-
Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 1.
-
-
-
-
-
-
19..16
-
-
RFDC_INFO_XTRA_RESAMP_DB1 (initialvalue=1)
-
Additional resampling happening outside the RFDC for daughterboard 0.
-
-
-
-
-
-
15..10
-
-
Reserved
-
-
-
-
-
-
-
9..7
-
-
RFDC_INFO_SPC_TX (initialvalue=1)
-
Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 0.
-
-
-
-
-
-
6..4
-
-
RFDC_INFO_SPC_RX (initialvalue=1)
-
Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 0.
-
-
-
-
-
-
3..0
-
-
RFDC_INFO_XTRA_RESAMP (initialvalue=1)
-
Additional resampling happening outside the RFDC for daughterboard 0.
This register is defined in HDL source file rfdc_timing_control.v.
-
-
-
-
-
-Gearbox reset control register.
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..8
-
-
Reserved
-
-
-
-
-
-
-
7..2
-
-
Reserved
-
-
-
-
-
-
-
1w
-
-
DAC_RESET (Strobe)
-
This reset is for the gearbox on the DAC data path that is used to
- move data from one clock domain to another outside the RFDC. Write
- a 1 to this bit to send a reset pulse to the DAC gearbox.
-
-
-
-
-
-
0w
-
-
ADC_RESET (Strobe)
-
This reset is for the gearbox on the ADC data path that is used to
- move data from one clock domain to another outside the RFDC. Write
- a 1 to this bit to send a reset pulse to the ADC gearbox.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI_REGMAP
-
-
-
SPI_REGS
-
-
This register map is present for each SPI master.
-
For information about the register content and the way to interact with the core see the
-documentation
-of the SPI master from opencores used internally.
-
The core is configured to operate with 16 slave signal signals, up to 128 bits per transmission and 8 bit clock divider.
-Only 64 bits of data are available via this register interface.
-
For the different SPI modes use the following table to derive the bits in CONTROL register. Only option 0 (CPOL=0, CPHA=0) has been tested.
This register is defined in HDL source file uhd_regs.v.
-
-
-
-
-
-
-
-
-
-
-
-
Bits
Name
-
-
-
31..16
-
-
pause_clear
-
-
If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause.
-Pause clear must be less than pause set or terrible things will happen.
-The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only
-used with 100Gb ethernet
-
-
-
-
-
-
15..0
-
-
pause_set
-
-
If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only
-used with 100Gb ethernet
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VERSIONING_REGS_REGMAP
-
-
VERSIONING_CONSTANTS
-
-
-
-
-
CPLD_IFC_VERSION Enumeration
-CPLD interface module.
- For guidance on when to update these revision numbers,
- please refer to the register map documentation accordingly:
-
- This enumerated type is defined in HDL source file cpld_interface_regs.v.
-
-
-
-
-
-
-
-
DB_GPIO_IFC_VERSION Enumeration
-Daughterboard GPIO interface.
- For guidance on when to update these revision numbers,
- please refer to the register map documentation accordingly:
-
- This enumerated type is defined in HDL source file rf_core_400m.v.
-
-
-
-
-
-
-
VERSIONING_REGS
-
-
-
-
-
COMPONENTS_INDEXES Enumeration
-This enum contains indexes for all the components in the X410
- (both common and app-specific) which version information is
- desired to be available for compatibility tracking purposes.
-
-
Description
Index range
Max # of components
-
Common components
0 to 23
24
-
UHD-specific components
24 to 43
20
-
LV-specific components
44 to 63
20
-
-
-
-
-
Value
-
Name
-
-
-
-
-
-
0
-
-
-
FPGA_VERSION_INDEX
-
-
-
-
-
-
-
-
1
-
-
-
CPLD_IFC_INDEX
-
-
-
-
-
-
-
-
2
-
-
-
DB0_RF_CORE_INDEX
-
-
-
-
-
-
-
-
3
-
-
-
DB1_RF_CORE_INDEX
-
-
-
-
-
-
-
-
4
-
-
-
DB0_GPIO_IFC_INDEX
-
-
-
-
-
-
-
-
5
-
-
-
DB1_GPIO_IFC_INDEX
-
-
-
-
-
-
-
-
- This enumerated type is defined in HDL source file x4xx_versioning_regs.v.
-
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x10000A0C00 + i*0x10
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file x4xx_versioning_regs.v.
-It uses RegType VERSION_TYPE which is defined in HDL source file x4xx_versioning_regs.v.
-
-
-
-
-
-Component's current version.
- This register contains the current component's version implemented in HDL.
- The current version shall be used to detect a component being too
- old for the driver/software:
- SW oldest compatible version > Component's current version --> Component is too old.
-
-
-
-
-
Bits
Name
-
-
-
31..23
-
-
MAJOR (initialvalue=0)
-
Major number (max = 511): an increase reflects a breaking change.
- IMPORTANT!MAJOR must always remain in sync between the component's
- CURRENT_VERSION and OLDEST_COMPATIBLE_VERSION registers.
a new feature is added to the component, which does not conflict with the driver.
-
minor implementation changes were made to the component which are worth tracking.
-
the component has added new bitfields/registers that do not require software interaction
- (i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to
- previously undefined bits).
-
Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
- but that should not impact the component's behavior
- Eventually, this number is intended to be automatically incremented for any new build.
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x10000A0C04 + i*0x10
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file x4xx_versioning_regs.v.
-It uses RegType VERSION_TYPE which is defined in HDL source file x4xx_versioning_regs.v.
-
-
-
-
-
-Component's oldest compatible version.
- This register contains the oldest compatible component's version, that is the oldest
- component's implementation that is compatible with the current implementation.
- The oldest compatible version shall be used to detect a component being too
- new for the driver/software:
- SW current version < Component's oldest compatible version --> Component is too new.
-
-
-
-
-
Bits
Name
-
-
-
31..23
-
-
MAJOR (initialvalue=0)
-
Major number (max = 511): an increase reflects a breaking change.
- IMPORTANT!MAJOR must always remain in sync between the component's
- CURRENT_VERSION and OLDEST_COMPATIBLE_VERSION registers.
a new feature is added to the component, which does not conflict with the driver.
-
minor implementation changes were made to the component which are worth tracking.
-
the component has added new bitfields/registers that do not require software interaction
- (i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to
- previously undefined bits).
-
Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
- but that should not impact the component's behavior
- Eventually, this number is intended to be automatically incremented for any new build.
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x10000A0C08 + i*0x10
-
-
-
-
-
-
-
-
-
-
-
Initial Value not specified
-
-
-
This register is defined in HDL source file x4xx_versioning_regs.v.
-It uses RegType TIMESTAMP_TYPE which is defined in HDL source file x4xx_versioning_regs.v.
-
-
-
-
-
-Component's versions update time.
- This register provides the time stamp for the last modification to
- the component's versions (current & oldest compatible).
- The time stamp is provided in hexadecimal format: 0xYYMMDDHH.
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
YY
-
This is the year number after 2000 (e.g. 2019 = 0x19).
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x10000A0C0C + i*0x10
-
-
-
-
-
-
-
-
-
-
-
Initial Value not specified
-
-
-
This register is defined in HDL source file x4xx_versioning_regs.v.
-It uses RegType RESERVED_TYPE which is defined in HDL source file x4xx_versioning_regs.v.
-
-
-
-
-
-Reserved.
-
-
-
-
-
-
-
-
-
-
-
-
-
XGE_MAC_REGMAP
-
-
-
OPENCORE_XGE_REGISTERS
-
-
10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf
-
-
-
-
-
-
\ No newline at end of file
diff --git a/top/x400/doc/X440/X440_FPGA.htm b/top/x400/doc/X440/X440_FPGA.htm
index bdefa98..ce8ecd6 100644
--- a/top/x400/doc/X440/X440_FPGA.htm
+++ b/top/x400/doc/X440/X440_FPGA.htm
@@ -1,10 +1,26461 @@
-
-
- X440_FPGA
-
-
-
\ No newline at end of file
+
+
+
+
+
+ X440_FPGA
+
+
+
+
+
+
+ This content is intended solely for use by core team members of the 'X440_FPGA' project.
+ Do not distribute or otherwise forward this content. If you believe you have acquired
+ access to this content in error, delete it immediately and notify the sender that you
+ are not intended to have access to this content.
+ This is the main AXI4-Lite master interface that the PS
+ exposes to the kernel to interact with the FPGA fabric.
+ There are multiple endpoints connected to this interface.
+
+
+ This port is defined in HDL source file x440_rfdc_regs.v.
+
+ This is the SPI1 interface
+ (see Zynq UltraScale+ Devices Register Reference)
+ of the PS.
+ With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.
+ The request format on SPI is defined as.
+ Write request:
+
+
1'b1 = write
+
15 bit address
+
32 bit data (MOSI)
+
8 bit processing gap
+
5 bit padding
+
1 bit ack
+
2 bit status
+
+ Read request:
+
+
1'b0 = read
+
15 bit address
+
8 bit processing gap
+
32 bit data (MISO)
+
5 bit padding
+
1 bit ack
+
2 bit status
+
+
+
+ This port is defined in HDL source file x440_rfdc_regs.v.
+
This is the map for the register space that the Processing System's
+M_AXI_HPM0_FPD port (AXI4 master interface) has access to.
+This port has a 40-bit address bus.
+ This is the map for the registers that the CORE_REGS window has access to
+ from the ARM_AXI_HPM0_FPD port.
+
+ The registers contained here conform the mboard-regs node that MPM uses
+ to manage general FPGA control/status calls, such as versioning,
+ timekeeper, GPIO, etc.
+
+ The following diagram shows how the communication bus interacts with the
+ modules in CORE_REGS.
+
+
+
+ Registers to control the SPI clock frequency of the CPLD interfaces.
+ The resulting clock frequency is calculated by .
+
+ Note that the PLL Reference Clock (PRC) is depending on the RF clocks.
+
+
+
+
+
+
+ This register is defined in HDL source file cpld_interface_regs.v.
+
+
+
+
+
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..8
+
+
Reserved
+
+
+
+
+
+
7..1
+
+
Reserved
+
+
+
+
+
+
0
+
+
IPASS_ENABLE_TRANSFER
+
If 1 enables the forwarding of iPass cable present signal to MB CPLD
+ using ctrlport requests. On change from 0 to 1 the current status is
+ transferred to the MB CPLD via SPI ctrlport request initially.
+ This register is defined in HDL source file x4xx_gpio_spi.v.
+
+
+
+
+ Starts a SPI transaction
+
+
+
+
Bits
Name
+
+
+
+
31..0w
+
+
SPI_DATA (initialvalue=0)
+
Payload to be sent for the SPI transaction. If the payload is shorter than 32 bits,
+ it must be aligned to the MSbs in this field. LSbs are ignored in this scenario.
+ Registers to control the GPIO buffer direction on the FPGA connected to
+ the DIO board. Further registers enable different sources to control and
+ read the GPIO lines as master. The following diagram shows how source
+ selection multiplexers are arranged, as well as an indicator for the
+ register that control them.
+
+ Make sure the GPIO lines between FPGA and GPIO board are not driven by
+ two drivers. Set the DIO registers in PS_CPLD_BASE_REGMAP appropriately.
+
+
+
+
+
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Sets whether the DIO signal line is driven by this register interface
+ or the user application.
+ 0 = user application is master, 1 = output of SW_DIO_CONTROL is master
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Set the direction of FPGA buffer connected to DIO ports on the DIO board.
+ Each bit represents one signal line. 0 = line is an input to the FPGA,
+ 1 = line is an output driven by the FPGA.
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls the values on each DIO signal line in case the line master is
+ set to PS in DIO_MASTER_REGISTER.
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls whether the DIO lines reflect the state of DIO_MASTER_REGISTER
+ or the radio blocks. 0 = DIO_MASTER_REGISTER,
+ 1 = Radio block output(DIO_OVERRIDE)
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls which radio block to use the ATR state from to determine the
+ state of the DIO lines.
+ 0 = Radio#0
+ 1 = Radio#1
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls which of the two available digital interfaces controls the DIO lines.
+ 0 = Digital interface from Radio#0,
+ 1 = Digital Interface from Radio#1.
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls whether the radio input to the DIO_SOURCE_REGISTER mux
+ connects to the ATR control or a Digital interface block. The output
+ of the mux controlled by this bit goes to DIO_SOURCE_REGISTER.
+ 0 = Drive the ATR state(RADIO_SOURCE_REGISTER), 1 = Drive
+ Digital interface block(Output of INTERFACE_DIO_SELECT).
+
+ This register is defined in HDL source file x4xx_dio.v.
+ It uses RegType DIO_CONTROL_REG which is
+ defined in HDL source file x4xx_dio.v.
+
+
+
+
+ Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls which source is forwarded to the DIO_MASTER_REGISTER mux.
+ This configuration is applied independently for each DIO line.
+ 0 = MPM Ctrlport endpoint, 1 = PS Netlist DIO signal.
+
+ This is the map that the nixge driver uses in Ethernet DMA to
+ move data between the Processing System's architecture and the fabric.
+ This map is a combination of two main components: a Xilix AXI DMA engine
+ and some registers for MAC/PHY control.
+
+
+
+
+ This window is defined in HDL source file common_regs.v.
+
+
+
+
+ Refer to Xilinx' AXI DMA v7.1 IP product guide for further
+ information on this register map:
+ https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
+
+ This register is defined in HDL source file x4xx_global_regs.v.
+
+
+
+
+ Control register for clocking resources.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
PPS_BRC_DELAY
+
Number of base reference clock cycles from appearance of the PPS
+ rising edge to the occurrence of the aligned edge of base reference
+ clock and PLL reference clock at the sample PLL output. This number
+ is the sum of the actual value based on PLL_SYNC_DELAY (also
+ accumulate the fixed amount of clock cycles) and if any the number of
+ cycles the SPLL requires from issuing of the SYNC signal to the
+ aligned edge (with LMK04832 = 0).
+ The number written to this register has to be reduced by 1 due to
+ HDL implementation.
+
+
+
+
+
23..16
+
+
PLL_SYNC_DELAY
+
Due to the HDL implementation the rising edge of the SYNC signal for
+ the LMK04832 is generated 2 clock cycles after the PPS rising edge.
+ This delay can be further increased by setting this delay value
+ (e.g. PLL_SYNC_DELAY=3 will result in a total delay of 5 clock cycles).
+ In case two X400 devices are connected using the PPS and reference clock the master delay value needs to be 3 clock cycles
+ higher than the slave delay value to align the LMK sync edges in time.
Assertion triggers the SYNC signal generation for LMK04832 after the next appearance of the PPS rising edge.
+ There is no self reset on this trigger.
+ Keep this trigger asserted until PLL_SYNC_DONE is asserted.
+
+
+
+
+
7..6
+
+
Reserved
+
+
+
+
+
+
5..4
+
+
TRIGGER_IO_SELECT (initialvalue=TRIG_IO_INPUT)
+
IMPORTANT! SW must ensure any TRIG_IO consumers (downstream devices) ignore
+ and/or re-sync after enabling this port, since the output-enable is basically
+ asynchronous to the actual TRIG_IO driver.
+
+
+
+ The values for this bitfield are in the TRIG_IO_ENUM table.
+ (show herehide)
+
+
+
+
+
+
+
+
+
Value
+
Name
+
+
+
+
+
0
+
+
+
+ TRIG_IO_INPUT
+
+
+
+
+
+
+
+
1
+
+
+
+ TRIG_IO_PPS_OUTPUT
+
+
+
+
+
+
+ This enumerated type is defined in HDL source file x4xx_global_regs.v.
+
+
+
+
+
+
+
+
+
+
3r
+
+
REFCLK_LOCKED
+
RESERVED. This bit is not implemented on X4xx and reads as 0.
+
+
+
+
+
2
+
+
REF_SELECT
+
RESERVED. This bit is not implemented on X4xx and reads as 0.
+
+
+
+
+
1..0
+
+
PPS_SELECT (initialvalue=PPS_INT_25MHZ)
+
Select the source of the PPS signal.
+ For the internal generation the value depending on the base reference clock has to be chosen.
+ The external reference is taken from the PPS_IN pin and is independent of the base reference clock.
+
+
+
+ The values for this bitfield are in the PPS_ENUM table.
+ (show herehide)
+
+
+
+
+
+
+
+
+
Value
+
Name
+
+
+
+
+
0
+
+
+
+ PPS_INT_25MHZ
+
+
+
+
+
+
+
+
1
+
+
+
+ PPS_INT_10MHZ
+
+
+
+
+
+
+
+
2
+
+
+
+ PPS_EXT
+
+
+
+
+
+
+ This enumerated type is defined in HDL source file x4xx_global_regs.v.
+
+ This register is defined in HDL source file x4xx_global_regs.v.
+
+
+
+
+ Control registers for PPS generation.
+
+
+
+
Bits
Name
+
+
+
+
31
+
+
PPS_RC_ENABLED
+
Enables the PPS signal in radio clock domain. Please make sure that
+ the values of PPS_BRC_DELAY, PPS_PRC_DELAY, PRC_RC0_DIVIDER and
+ PRC_RC1_DIVIDER are set before enabling this bit. It is recommended
+ to disable the PPS for changes on the other values. Use a wait time of
+ at least 1 second before changing this value to ensure the values are
+ stable for the next PPS edge.
+
+
+
+
+
30..26
+
+
Reserved
+
+
+
+
+
+
25..0
+
+
PPS_PRC_DELAY
+
The number of PLL reference clock cycles from one aligned edge to the
+ desired aligned edge to issue the PPS in radio clock domain. This
+ delay is configurable to any aligned edge within a maximum delay of 1
+ second (period of PPS).
+ The value written to the register has to be reduced by 5 due to
+ HDL implementation.
+ This register is defined in HDL source file x4xx_global_regs.v.
+
+
+
+
+ Control registers for PPS clock crossing to the radio clock domain.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..21
+
+
Reserved
+
+
+
+
+
+
20..16
+
+
PRC_RC1_DIVIDER
+
Clock multiplier used to generate radio clock 1 from PLL reference clock.
+ The value written to the register has to follow the following formula:
+ PRC_RC1_DIVIDER = (RADIO_CLK_1 / PRC_CLK) * 2 - 2
+
+
+
+
+
15..8
+
+
Reserved
+
+
+
+
+
+
7..5
+
+
Reserved
+
+
+
+
+
+
4..0
+
+
PRC_RC0_DIVIDER
+
Clock multiplier used to generate radio clock 0 from PLL reference clock.
+ The value written to the register has to follow the following formula:
+ PRC_RC0_DIVIDER = (RADIO_CLK_0 / PRC_CLK) * 2 - 2
+ This register is defined in HDL source file x4xx_global_regs.v.
+
+
+
+
+ Status register for mfg_test functions.
+
+
+
+
Bits
Name
+
+
+
+
31..26
+
+
Reserved
+
+
+
+
+
+
25..0
+
+
MFG_TEST_FPGA_AUX_REF_FREQ
+
Report the time between rising edges on the FPGA_REF_CLK
+ input port in 40 MHz Clock ticks. If the count extends
+ to 1.2 seconds without an edge, the value reported is set
+ to zero.
+ This register is defined in HDL source file x4xx_gpio_atr.v.
+ It uses RegType GPIO_ATR_STATE which is
+ defined in HDL source file x4xx_gpio_atr.v.
+
+
+
+
+ Holds a single bit setting for GPIO lines in both ports for a particular ATR sate
+Describes GPIO behavior for the different ATR states. When ATR_OPTION
+ is set to use the DB states, TX and RX states for RF0 and RF1 are
+ combined to create a single vector. This creates 16 different
+ combinations, each with its own register. When ATR_OPTION is set to
+ classic ATR, offsets 0x00-0x03 in this register group will be driven
+ in accordance with the state of RF0, and offsets 0x04-0x07 will be
+ driven in accordance with the state of RF1.
+ CLASSIC ATR MAPPING: Idle[RF0:0x00; RF1:0x04], RX[RF0:0x01; RF1:0x05],
+ TX[RF0:0x02; RF1:0x06], FDX[RF0:0x03; RF1:0x07]
+
+ This register is defined in HDL source file x4xx_gpio_atr.v.
+
+
+
+
+ Controls the RF state mapping of each GPIO line when classic
+ ATR mode is active.
+
+
+
+
Bits
Name
+
+
+
+
31..28
+
+
Reserved
+
+
+
+
+
+
27..16
+
+
RF_SELECT_B (initialvalue=0)
+
Set which RF channel's state to reflect in the pins of
+ HDMI connector B when ATR_OPTION is set to classic ATR.
+ Controlled in a per-pin basis.
+ 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03)
+ 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)
+
+
+
+
+
15..12
+
+
Reserved
+
+
+
+
+
+
11..0
+
+
RF_SELECT_A (initialvalue=0)
+
Set which RF channel's state to reflect in the pins for
+ HDMI connector A when ATR_OPTION is set to classic ATR.
+ Controlled in a per-pin basis.
+ 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03)
+ 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)
+ This register is defined in HDL source file x4xx_gpio_atr.v.
+
+
+
+
+ Controls whether GPIO lines use the TX and RX state of an RF channel
+ (Classic ATR) or the daughterboard state the selector for the
+ ATR_STATE.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..8
+
+
Reserved
+
+
+
+
+
+
7..1
+
+
Reserved
+
+
+
+
+
+
0
+
+
ATR_OPTION (initialvalue=0)
+
Sets the scheme in which RF states in the radio will control GPIO
+ lines. 0 = DB state is used. RF states are combined and the
+ GPIO state is driven based on all 16 ATR_STATE registers.
+ 1 = Each RF channel has its separate ATR state(Classic ATR).
+ Use register CLASSIC_ATR_CONFIG to indicate the RF channel
+ to which each GPIO line responds to.
+ Each channel in the FBX daughterboard has 3 LEDs. TXRX Red/Green LEDs and RX2 Green LED.
+ This register map describes how to control the behavior of the 3 LEDs.
+ There are three supported control schemes for these LEDs:
+
+
ATR Disabled - Single persistent state.
+
Classic ATR - Each channel's LEDs depend on the transmission state
+ of the respective channel.
+
DB State - Each channel's LEDs depend on the transmission state
+ of all channels in this radio.
+ This register is defined in HDL source file led_atr_control.v.
+ It uses RegType LED_ATR_STATE which is
+ defined in HDL source file led_atr_control.v.
+
+
+
+
+ Holds the value for the control lines of each channel's LEDs
+ for a particular ATR sate
+Describes led behavior for the different ATR states. When LED0_ATR_OPTION
+ is set to use the DB states, TX and RX states for LED0-LED3 are
+ combined to create a single vector. This creates 256 different
+ combinations, each with its own register. When LED0_ATR_OPTION is set to
+ classic ATR, the first 4 offsets in this register group will be driven
+ in accordance with the state of RF0.
+ CLASSIC ATR MAPPING: Idle[RF0: TX=0, RX=0], RX[RF0: TX=0, RX=1,
+ TX[RF0: TX=1, RX=0], FDX[RF0: TX=1, RX=1]
+
+ This register is defined in HDL source file led_atr_control.v.
+ It uses RegType LED_ATR_STATE which is
+ defined in HDL source file led_atr_control.v.
+
+
+
+
+ Holds the value for the control lines of each channel's LEDs
+ for a particular ATR sate
+Describes led behavior for the different ATR states. When LED1_ATR_OPTION
+ is set to use the DB states, TX and RX states for LED0-LED3 are
+ combined to create a single vector. This creates 256 different
+ combinations, each with its own register. When LED1_ATR_OPTION is set to
+ classic ATR, the first 4 offsets in this register group will be driven
+ in accordance with the state of RF1.
+ CLASSIC ATR MAPPING: Idle[RF1: TX=0, RX=0], RX[RF1: TX=0, RX=1,
+ TX[RF1: TX=1, RX=0], FDX[RF1: TX=1, RX=1]
+
+ This register is defined in HDL source file led_atr_control.v.
+ It uses RegType LED_ATR_STATE which is
+ defined in HDL source file led_atr_control.v.
+
+
+
+
+ Holds the value for the control lines of each channel's LEDs
+ for a particular ATR sate
+Describes led behavior for the different ATR states. When LED2_ATR_OPTION
+ is set to use the DB states, TX and RX states for LED0-LED3 are
+ combined to create a single vector. This creates 256 different
+ combinations, each with its own register. When LED2_ATR_OPTION is set to
+ classic ATR, the first 4 offsets in this register group will be driven
+ in accordance with the state of RF2.
+ CLASSIC ATR MAPPING: Idle[RF2: TX=0, RX=0], RX[RF2: TX=0, RX=1,
+ TX[RF2: TX=1, RX=0], FDX[RF2: TX=1, RX=1]
+
+ This register is defined in HDL source file led_atr_control.v.
+ It uses RegType LED_ATR_STATE which is
+ defined in HDL source file led_atr_control.v.
+
+
+
+
+ Holds the value for the control lines of each channel's LEDs
+ for a particular ATR sate
+Describes led behavior for the different ATR states. When LED3_ATR_OPTION
+ is set to use the DB states, TX and RX states for LED0-LED3 are
+ combined to create a single vector. This creates 256 different
+ combinations, each with its own register. When LED3_ATR_OPTION is set to
+ classic ATR, the first 4 offsets in this register group will be driven
+ in accordance with the state of RF3.
+ CLASSIC ATR MAPPING: Idle[RF3: TX=0, RX=0], RX[RF3: TX=0, RX=1,
+ TX[RF3: TX=1, RX=0], FDX[RF3: TX=1, RX=1]
+
+ This register is defined in HDL source file led_atr_control.v.
+
+
+
+
+ Controls whether switch control lines use the TX and RX state of
+ their respective channel (Classic ATR) or the daughterboard state
+ to select which state to use from values set in LED_ATR_STATE registers.
+ For each particular bit:
+ 0: Use DB state for ATR
+ 1: Classic ATR mode.
+
This register map is available using the PL CPLD SPI interface.
+All protocol masters controller by this register map are running with a clock frequency of 50 MHz.
+ This register is defined in HDL source file uhd_regs.v.
+
+
+
+
+
+
Definition of this register depends on Protocol
+
10GBE
+
READ - Status
+
+
0 = status_crc_error
+
1 = status_fragment_error
+
2 = status_txdfifo_ovflow
+
3 = status_txdfifo_udflow
+
4 = status_rxdfifo_ovflow
+
5 = status_rxdfifo_udflow
+
6 = status_pause_frame_rx
+
7 = status_local_fault
+
8 = status_remote_fault
+
+
WRITE - Ctl
+
+
0 = ctrl_tx_enable
+
+
100 GBE
+
READ - Status
+
+
0 = tx_ovfout - Sets if TX overflow reported by CMAC
+ (Stays set till MAC is reset). This is a fatal error
+
1 = tx_unfout - Sets if TX underflow reported by CMAC
+ (Stays set till MAC is reset). This is a fatal error
+
2 = stat_rx_aligned - goes high when CMAC has finished
+ alignment, and is ready to start reception of traffic.
+
3 = mac_dropped_packet - If the mac RX wants to push data(TVALID)
+ but upstream is trying to hold(TREADY)off we drop a packet.
+ Upstream circuitry should detect this when traffic is forked
+ between CHDR and CPU, so this bit will only set if there is a
+ HW design error.
+
4 = auto_config_done - This bit goes high when the auto_config
+ state machine finishes operation. It is very similiar to
+ stat_rx_alligned, but waits for extra writes which occur
+ after allignement to complete.
+
24:16 = pause_mask - readable version of pause_mask bellow.
+
+
WRITE - Ctl
+
+
0 = auto_enable - Defaults to ON after reset - Enables a
+ state machine that performs CMAC register writes to
+ bring up the MAC without SW intervention.
+
24:16 = pause_mask - A second layer of enables(the first being
+ register in the CMAC) on the pause_request mechanic. Bits
+ 7:0 of enable pause on PFC7:0. Bit 8 enables global pause
+ request (not priority controlled). The mask is used for TX
+ and RX.
+ This register is defined in HDL source file pl_cpld_regs.v.
+
+
+
+
+ This register returns (in YYMMDDHH format) the oldest revision
+ that is still compatible with this one. Compatible means that
+ registers or register bits may have been added, but not
+ modified or deleted (see OLDEST_CPLD_REVISION of CONSTANTS_REGMAP).
+
+ This register map is available from the PS via AXI and MPM endpoint.
+ Its size is 128K (17 bits). Only the 17 LSBs are used as address in this documentation.
+
+
+
+
+ This is a regmap to document the different ports that have access to the PS system memory.
+ Each port may have different restrictions on system memory. See the corresponding window
+ for details
+
+
+
+
+ This window is defined in HDL source file common_regs.v.
+
+
+
+
+ The HPC0 port of the PS is used for general purpose cache-coherent accesses
+ to the PS system memory. Different applications may use it for different
+ purposes. Its access is configured as follows:
+
+ This window is defined in HDL source file common_regs.v.
+
+
+
+
+ The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave
+ interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx.
+ Its access is configured as follows:
+
+ Registers to control the GPIO buffer direction on the DIO board connected to the FPGA.
+ Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers.
+ Set the direction in the FPGA's DIO register appropriately.
+
+
+
+
+
+
+ This register is defined in HDL source file ps_cpld_regs.v.
+
+
+
+
+ Set the direction of FPGA buffer connected to DIO ports on the DIO board.
+ Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA.
+
+ This register is defined in HDL source file ps_cpld_regs.v.
+
+
+
+
+ Register to control the PL part DB SPI connection and reset generation.
+ The DB connection is clocked with PLL reference clock. Ensure this clock is stable
+ and enabled before starting any SPI request.
+ The PLL reference clock can be disabled if both DB connections are disabled or inactive.
+ To enable the DB connection, enable clock with one write access and release
+ reset with the next write access.
+ To disable the DB connection, assert reset with one write access and
+ disable clocks with the next write access.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..22
+
+
Reserved
+
+
+
+
+
+
21w
+
+
ASSERT_RESET_DB1
+
Writing with this flag set asserts reset for DB 1 (overrides RELEASE_RESET_DB1)
+
+
+
+
+
20w
+
+
ASSERT_RESET_DB0
+
Writing with this flag set asserts reset for DB 0 (overrides RELEASE_RESET_DB0)
+
+
+
+
+
19..18
+
+
Reserved
+
+
+
+
+
+
17w
+
+
RELEASE_RESET_DB1
+
Writing with this flag set releases DB 1 reset. (may be overwritten by ASSERT_RESET_DB1)
+
+
+
+
+
16w
+
+
RELEASE_RESET_DB0
+
Writing with this flag set releases DB 0 reset. (may be overwritten by ASSERT_RESET_DB0)
+
+
+
+
+
15
+
+
Reserved
+
+
+
+
+
+
14w
+
+
DISABLE_PLL_REF_CLOCK
+
Writing with this flag set disables the PLL reference clock (overrides ENABLE_PLL_REF_CLOCK). Assert this flag to reconfigure the clock.
+
+
+
+
+
13w
+
+
DISABLE_CLOCK_DB1
+
Writing with this flag set disables DB 1 clock forwarding (overrides ENABLE_CLOCK_DB1)
+
+
+
+
+
12w
+
+
DISABLE_CLOCK_DB0
+
Writing with this flag set disables DB 0 clock forwarding (overrides ENABLE_CLOCK_DB0)
+
+
+
+
+
11
+
+
Reserved
+
+
+
+
+
+
10w
+
+
ENABLE_PLL_REF_CLOCK
+
Writing with this flag set enables the PLL reference clock. Assert this flag after PLL reference clock is stable. (may be overwritten by DISABLE_PLL_REF_CLOCK)
+
+
+
+
+
9w
+
+
ENABLE_CLOCK_DB1
+
Writing with this flag set enables DB 1 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB1)
+
+
+
+
+
8w
+
+
ENABLE_CLOCK_DB0
+
Writing with this flag set enables DB 0 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB0)
+
+
+
+
+
7..6
+
+
Reserved
+
+
+
+
+
+
5r
+
+
DB1_RESET_ASSERTED
+
Indicates that reset is asserted for DB 1.
+
+
+
+
+
4r
+
+
DB0_RESET_ASSERTED
+
Indicates that reset is asserted for DB 0.
+
+
+
+
+
3
+
+
Reserved
+
+
+
+
+
+
2r
+
+
PLL_REF_CLOCK_ENABLED
+
Indicates if the PLL reference clock for the PL interface is enabled.
+ This register is defined in HDL source file ps_cpld_regs.v.
+
+
+
+
+ This register returns (in YYMMDDHH format) the oldest revision
+ that is still compatible with this one. Compatible means that
+ registers or register bits may have been added, but not
+ modified or deleted (see OLDEST_CPLD_REVISION of CONSTANTS_REGMAP).
+
+ This register is defined in HDL source file ps_power_regs.v.
+
+
+
+
+ Controls the power supplies for the iPass connectors.
+
+
+
+
Bits
Name
+
+
+
+
31r
+
+
IPASS_POWER_FAULT1
+
Asserted signal indicates a power fault in power switch for iPass
+ connector 1. Sticky bit. Asserted on occurrence. Reset using
+ IPASS_CLEAR_POWER_FAULT1.
Asserted signal indicates a power fault in power switch for iPass
+ connector 0. Sticky bit. Asserted on occurrence. Reset using
+ IPASS_CLEAR_POWER_FAULT0.
+ Each radio's CtrlPort peripheral interface is divided into the
+ following memory spaces. Note that the CtrlPort peripheral interface
+ starts at offset 0x80000 in the RFNoC Radio block's register space.
+ The following diagram displays the distribution of the CtrlPort
+ interface to the different modules it interacts with.
+
+
+
+
+ These registers are used to upload and verify a new primary image to the
+ Max 10 FPGA on-chip flash when configured to support dual configuration
+ images. The steps below outline the process of verifying/preparing the
+ new image to be written, erasing the current image, writing the new
+ image, and verifying the new image was successfully written.
+
Prepare the data...
+
The Max 10 FPGA build should generate a *cfm0_auto.rpd
+ file The *.rpd file is a "raw programming
+ data" file holding all data related to the
+ configuration image (CFM0). There are two
+ important items to note regarding the addresses.
+ First the *rpd data uses byte addresses.
+ Second, the start/end addresses defined by
+ FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses
+
As a sanity check, verify the size of the raw
+ programming data for CFM0 correspond to the address
+ range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by
+ reading the values from FLASH_CFM0_START_ADDR_REG and
+ FLASH_CFM0_END_ADDR, subtract both values, add one and
+ multiply by four.
+
+
Having passed the sanity check the *.rpd data must
+ now be manipulated into the form required by Altera's
+ on-chip flash IP. Two operations must be performed.
+ First the data must be converted from bytes to 32-bit
+ words. Second the bit order must be reversed. This is
+ illustrated in in the following table which shows byte
+ address and data from the *.rpd file compared to the
+ word address and data to be written to the on-chip
+ flash.
+
+
.Map Addr
.Map Data
Flash Addr
Flash Data
+
0x2B800
0x01
0xAC00
0x8040C020
+
0x2B801
0x02
+
0x2B802
0x03
+
0x2B803
0x04
+
0x2B804
0x05
0xAC01
0xA060E010
+
0x2B805
0x06
+
0x2B806
0x07
+
0x2B807
0x08
+
+
+
The resulting set of flash address data pairs should
+ be used when writing FLASH_ADDR_REG and
+ FLASH_WRITE_DATA_REG to update the CFM0 image.
+ However, prior to writing the new image the old image
+ must be erased.
+
+
+
+
Erase the current primary flash image...
+
Read FLASH_STATUS_REG and verify no error bits are
+ asserted and that all read, write, and erase operations
+ are idle.
+
Disable write protection of the flash by strobing the
+ FLASH_DISABLE_WP_STB bit of FLASH_CONTROL_REG.
+
+
Verify write protection is disabled and no errors are
+ present by reading FLASH_STATUS_REG.
+
Initiate the erase operation by setting
+ FLASH_ERASE_SECTOR and strobing FLASH_ERASE_STB of
+ FLASH_CONTROL_REG.
+
Poll the FLASH_ERASE_IDLE bit of
+ FLASH_STATUS_REG until it de-asserts indicating the
+ erase operation is complete, then verify the operation
+ was successful by checking that the FLASH_ERASE_ERR
+ bit is de-asserted. Erase operations are expected to
+ take a maximum of 350 msec. Upon completion of the erase
+ operation write protection will remain disabled.
+
+
Erase additional sectors as required (see
+ FLASH_ERASE_SECTOR for details) by restarting with first
+ step.
+
+
+
Write the new primary flash image...
+
Read FLASH_STATUS_REG and verify no error bits are
+ asserted, all read, write, and erase operations are
+ idle, and write protection is disabled.
+
Set the target address for the write to the Max 10
+ on-chip flash by writing value from
+ FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.
+
Set the data to be written to this address by writing
+ the new 32-bit word of the new image to
+ FLASH_WRITE_DATA_REG.
+
Initiate the write by strobing FLASH_WRITE_STB of
+ FLASH_CONTROL_REG.
+
Poll the FLASH_WRITE_IDLE bit of
+ FLASH_STATUS_REG until it de-asserts indicating the
+ write operation is complete, then verify the operation
+ was successful by checking that the FLASH_WRITE_ERR
+ bit is de-asserted. Write operations are expected to
+ take a maximum of 550 usec.
+
Upon completion of the write operation return to step
+ 2, incrementing the target address by one, and writing
+ the next 32-bit word to Max10FlashWriteDatReg. If this
+ was the last write, indicated by writing to
+ FLASH_PRIMARY_IMAGE_END_ADDR, proceed to the next step
+ to enable write protection.
+
After writing the new image enable write protection
+ by strobing the FLASH_ENABLE_WP_STB bit of
+ FLASH_CONTROL_REG.
+
+
+
Verify the new primary flash image...
+
Read FLASH_STATUS_REG and verify no error bits are
+ asserted and that all read, write, and erase operations
+ are idle.
+
Set the target address for the read in the Max 10
+ on-chip flash by writing value from
+ FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.
+
Initiate the read by strobing FLASH_READ_STB of
+ FLASH_CONTROL_REG.
+
Poll the FLASH_READ_IDLE bit of
+ FLASH_STATUS_REG until it de-asserts indicating the
+ read operation is complete, then verify the operation
+ was successful by checking that the FLASH_READ_ERR
+ bit is de-asserted. There is no guidance on exactly how
+ long reads take to complete, but they are expected to be
+ fairly quick. A very conservative timeout on this
+ polling would be similar to that used for write
+ operations.
+
Upon completion of the read operation the resulting
+ data returned by the on-chip flash will be available in
+ Max10FlashReadDatReg. Read this register, compare to
+ expected value previously written, and ensure they
+ match.
+
Return to step 2, incrementing the target
+ address by one. If this was the last read verification
+ is complete and no further action is required.
+
+
+
After the flash has been erased, programmed, and verified, a power
+ cycle is required for the new image to become active.
+
+ These values are the start and end address of the CFM image flash
+ sector from Intel's On-Chip Flash IP Generator.
+ Be aware that three different values exist per each of the two
+ supported MAX10 variants: 10M04 and 10M08
+ Note that the values given in the IP generator are byte based where
+ the values of this enum are U32 based (divided by 4).
+
+
+ This register is defined in HDL source file reconfig_engine.v.
+
+
+
+
+
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..17
+
+
Reserved
+
+
+
+
+
+
16
+
+
FLASH_MEM_INIT_ENABLED
+
This bit is asserted when the flash can hold an image with memory
+ initialization.
+
+
+
+
+
15..14
+
+
Reserved
+
+
+
+
+
+
13
+
+
FLASH_WRITE_ERR
+
This bit is asserted when write operation fails. Clear this error
+ by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In
+ the event of a write error...
+
the primary configuration image may be corrupted, and
+ power cycling the board may result unknown behavior.
+
write protection of the flash will automatically be
+ re-enabled.
+
attempts to disable write protection will be ignored.
+
attempts to read/write/erase the flash will be ignored.
+
+
+
+
+
12
+
+
FLASH_WRITE_IDLE
+
This bit is de-asserted when a write operation is in progress. Poll
+ this bit after strobing the FLASH_WRITE_STB bit of
+ FLASH_CONTROL_REG to determine when the write operation has
+ completed, then check the FLASH_WRITE_ERR bit to verify the
+ operation was successful.
+
+
+
+
+
11..10
+
+
Reserved
+
+
+
+
+
+
9
+
+
FLASH_ERASE_ERR
+
This bit is asserted when an erase operation fails. Clear this
+ error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In
+ the event of an erase error...
+
the primary configuration image may be corrupted, and
+ power cycling the board may result in unknown behavior.
+
write protection of the flash will automatically be
+ re-enabled.
+
attempts to disable write protection will be ignored.
+
attempts to read/write/erase the flash will be ignored.
+
+
+
+
+
8
+
+
FLASH_ERASE_IDLE
+
This bit is de-asserted when an erase operation is in progress. Poll
+ this bit after strobing the FLASH_ERASE_STB bit of
+ FLASH_CONTROL_REG to determine when the erase operation has
+ completed, then check the FLASH_ERASE_ERR bit to verify the
+ operation was successful.
+
+
+
+
+
7..6
+
+
Reserved
+
+
+
+
+
+
5
+
+
FLASH_READ_ERR
+
This bit is asserted when a read operation fails. Clear this error
+ by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the
+ event of a read error...
+
the data in FLASH_READ_DATA_REG is invalid.
+
attempts to disable write protection will be ignored.
+
attempts to read/write/erase the flash will be ignored.
+
+
+
+
+
4
+
+
FLASH_READ_IDLE
+
This bit is de-asserted when a read operation is in progress. Poll
+ this bit after strobing the FLASH_READ_STB bit of
+ FLASH_CONTROL_REG to determine when the read operation has
+ completed, then check the FLASH_READ_ERR bit to verify the
+ operation was successful.
+
+
+
+
+
3..1
+
+
Reserved
+
+
+
+
+
+
0
+
+
FLASH_WP_ENABLED
+
This bit is asserted when the flash is write protected and
+ de-asserted when write protection is disabled.
+
Write protection must be enabled prior to performing read
+ operations.
+
Write protection must be disabled prior to performing write and
+ erase operations.
+ This register is defined in HDL source file reconfig_engine.v.
+
+
+
+
+
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..11
+
+
Reserved
+
+
+
+
+
+
10w
+
+
CLEAR_FLASH_ERASE_ERROR_STB (Strobe)
+
Strobe this bit to clear an erase error.
+
+
+
+
+
9w
+
+
CLEAR_FLASH_WRITE_ERROR_STB (Strobe)
+
Strobe this bit to clear a write error.
+
+
+
+
+
8w
+
+
CLEAR_FLASH_READ_ERROR_STB (Strobe)
+
Strobe this bit to clear a read error.
+
+
+
+
+
7..5w
+
+
FLASH_ERASE_SECTOR (Strobe)
+
Defines the sector to be erased. Has to be set latest with the
+ write access which starts the erase operation by strobing
+ FLASH_ERASE_STB.
+ With 10M04 variants, if the flash is configured to support memory
+ initialization (see FLASH_MEM_INIT_ENABLED flag) the sectors 2
+ to 4 have to be erased. If the flag is not asserted only sector 4
+ has to be erased.
+ With 10M08 variants, the sectors to be erased are 3 to 5 when
+ using memory initialization or only sector 5 otherwise.
+
+
+
+
+
4w
+
+
FLASH_ERASE_STB (Strobe)
+
Strobe this bit to erase the primary Max10 configuration image
+ (CFM0).
+
Prior to strobing this bit verify no other write or erase
+ operations are in progress, write protection is disabled, and no
+ error bits are asserted by reading FLASH_STATUS_REG.
+
Attempts to erase the primary image while other write or erase
+ operations are in progress will be ignored.
+
Attempts to erase the primary image when write protection is
+ enabled will be ignored.
+
Strobing this bit and FLASH_WRITE_STB simultaneously will
+ result both the erase and the write operation being ignored, both
+ corresponding error bits being set, and write protection being
+ re-enabled.
+
After strobing this bit poll the FLASH_ERASE_IDLE and
+ FLASH_ERASE_ERR bits of FLASH_STATUS_REG to determine when
+ the erase operation is complete and if it was successful.
+
+
+
+
+
3w
+
+
FLASH_WRITE_STB (Strobe)
+
Strobe this bit to write the data contained in
+ FLASH_WRITE_DATA_REG to the flash address identified in
+ FLASH_ADDR_REG.
+
The flash must be erased before writing new data.
+
Prior to strobing this bit verify write protection is
+ disabled, no other write or erase operations are in progress, and
+ no error bits are asserted by reading FLASH_STATUS_REG.
+
Attempts to write data while other write or erase operations
+ are in progress will be ignored.
+
Attempts to write data with write protection enabled will be
+ ignored.
+
Strobing this bit and FLASH_ERASE_STB simultaneously will
+ result in both the write and erase operation being ignored,
+ both corresponding error bits being set, and write protection
+ being re-enabled.
+
After strobing this bit poll theMax10FlashWriteIdle and
+ FLASH_WRITE_ERR bits of FLASH_STATUS_REG to determine when
+ the write operation is complete and if it was successful.
+
+
+
+
+
2w
+
+
FLASH_READ_STB (Strobe)
+
Strobe this bit to read data from the flash address identified in
+ FLASH_ADDR_REG.
+
Prior to strobing this bit verify no read, write, or erase
+ operations are in progress, no error bits are asserted, and
+ write protection is enabled by reading FLASH_STATUS_REG.
+
Attempts to read data while other operations are in progress
+ or while write protection is disabled will be ignored.
+
After strobing this bit poll the FLASH_READ_IDLE and
+ FLASH_READ_ERR bits of FLASH_STATUS_REG to determine when
+ the read operation is complete and if it was successful.
+
Upon successful completion the data read from flash will be
+ available in FLASH_READ_DATA_REG.
+
+
+
+
+
1w
+
+
FLASH_DISABLE_WP_STB (Strobe)
+
Strobe this bit to disable write protection to the section of the
+ Max 10 on-chip flash storing the primary configuration image
+ (CFM0).
+
Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to
+ determine the current state of write protection.
+
Prior to strobing this bit verify no read operations are in
+ progress and no error bits are asserted by reading
+ FLASH_STATUS_REG.
+
Attempts to disable write protection while a read is in
+ progress will be ignored.
+
Attempts to disable write protection will be ignored if
+ this bit is strobed simultaneously with either FLASH_READ_STB
+ or FLASH_ENABLE_WP_STB.
+
Write protection must be disabled prior to performing erase or
+ write operations.
+
Upon completion of erase/write operations write protection
+ will remain disabled. When not actively erasing or writing a new
+ image write protection should be enabled to avoid data
+ corruption.
+
+
+
+
+
0w
+
+
FLASH_ENABLE_WP_STB (Strobe)
+
Strobe this bit to enable write protection to the section of the
+ Max 10 on-chip flash storing the primary configuration image
+ (CFM0).
+
Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to
+ determine the current state of write protection.
+
Prior to strobing this bit verify no write or erase operations
+ are in progress and no error bits are asserted by reading
+ FLASH_STATUS_REG.
+
Attempts to enable write protection while erase or write
+ operations are in progress will be ignored.
+
Write protection must be enabled prior to performing
+ read operations.
+
Write protection should be enabled after completing
+ write or erase operations to prevent data corruption.
+ This register is defined in HDL source file reconfig_engine.v.
+
+
+
+
+
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..17
+
+
Reserved
+
+
+
+
+
+
16..0
+
+
FLASH_ADDR
+
This field holds the target address for the next read or
+ write operation. Set this field prior to strobing the
+ FLASH_WRITE_STB and FLASH_READ_STB bits of
+ FLASH_CONTROL_REG. Valid addresses are defined by the
+ FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration.
+ Each channel in the FBX daughterboard has 4 switches in its path. 3 of these are HMC849A 2:1
+ switches and the last one is a PE42442 4:1 switch. The latter, as well as the enable lines for
+ all four switches are not considered time critical controls, and are hence driven by an I/O
+ expander controlled via I2C.
+ This register map describes how to control the behavior of the 3 HMC849A switches' control lines.
+ There are three supported control schemes for these switches:
+
+
ATR Disabled - Single persistent state.
+
Classic ATR - Each channel's switches depend on the transmission state
+ of the respective channel.
+
DB State - Each channel's switches depend on the transmission state
+ of all channels in this radio.
+ This register is defined in HDL source file rf_atr_control.v.
+ It uses RegType RF_ATR_STATE which is
+ defined in HDL source file rf_atr_control.v.
+
+
+
+
+ Holds the value for the control lines of each channel's switches
+ for a particular ATR sate
+Describes switch control behavior for the different ATR states. When RF0_ATR_OPTION
+ is set to use the DB states, TX and RX states for RF0-RF3 are
+ combined to create a single vector. This creates 256 different
+ combinations, each with its own register. When RF0_ATR_OPTION is set to
+ classic ATR, the first 4 offsets in this register group will be driven
+ in accordance with the state of RF0.
+ CLASSIC ATR MAPPING: Idle[RF0: TX=0, RX=0], RX[RF0: TX=0, RX=1,
+ TX[RF0: TX=1, RX=0], FDX[RF0: TX=1, RX=1]
+
+ This register is defined in HDL source file rf_atr_control.v.
+ It uses RegType RF_ATR_STATE which is
+ defined in HDL source file rf_atr_control.v.
+
+
+
+
+ Holds the value for the control lines of each channel's switches
+ for a particular ATR sate
+Describes switch control behavior for the different ATR states. When RF1_ATR_OPTION
+ is set to use the DB states, TX and RX states for RF0-RF3 are
+ combined to create a single vector. This creates 256 different
+ combinations, each with its own register. When RF1_ATR_OPTION is set to
+ classic ATR, the first 4 offsets in this register group will be driven
+ in accordance with the state of RF1.
+ CLASSIC ATR MAPPING: Idle[RF1: TX=0, RX=0], RX[RF1: TX=0, RX=1,
+ TX[RF1: TX=1, RX=0], FDX[RF1: TX=1, RX=1]
+
+ This register is defined in HDL source file rf_atr_control.v.
+ It uses RegType RF_ATR_STATE which is
+ defined in HDL source file rf_atr_control.v.
+
+
+
+
+ Holds the value for the control lines of each channel's switches
+ for a particular ATR sate
+Describes switch control behavior for the different ATR states. When RF2_ATR_OPTION
+ is set to use the DB states, TX and RX states for RF0-RF3 are
+ combined to create a single vector. This creates 256 different
+ combinations, each with its own register. When RF2_ATR_OPTION is set to
+ classic ATR, the first 4 offsets in this register group will be driven
+ in accordance with the state of RF2.
+ CLASSIC ATR MAPPING: Idle[RF2: TX=0, RX=0], RX[RF2: TX=0, RX=1,
+ TX[RF2: TX=1, RX=0], FDX[RF2: TX=1, RX=1]
+
+ This register is defined in HDL source file rf_atr_control.v.
+ It uses RegType RF_ATR_STATE which is
+ defined in HDL source file rf_atr_control.v.
+
+
+
+
+ Holds the value for the control lines of each channel's switches
+ for a particular ATR sate
+Describes switch control behavior for the different ATR states. When RF3_ATR_OPTION
+ is set to use the DB states, TX and RX states for RF0-RF3 are
+ combined to create a single vector. This creates 256 different
+ combinations, each with its own register. When RF3_ATR_OPTION is set to
+ classic ATR, the first 4 offsets in this register group will be driven
+ in accordance with the state of RF3.
+ CLASSIC ATR MAPPING: Idle[RF3: TX=0, RX=0], RX[RF3: TX=0, RX=1,
+ TX[RF3: TX=1, RX=0], FDX[RF3: TX=1, RX=1]
+
+ This register is defined in HDL source file rf_atr_control.v.
+
+
+
+
+ Controls whether switch control lines use the TX and RX state of
+ their respective channel (Classic ATR) or the daughterboard state
+ to select which state to use from values set in RF_ATR_STATE registers.
+ For each particular bit:
+ 0: Use DB state for ATR
+ 1: Classic ATR mode.
+
+ Each channel in the FBX daughterboard has 4 switches in its path. 3 of these are HMC849A 2:1
+ switches and the last one is a PE42442 4:1 switch. The latter, as well as the enable lines for
+ all four switches are not considered time critical controls, and are hence driven by a
+ TCA6416A I/O expander controlled via I2C.
+ This register map controls that I/O expander. The first 6 registers in
+ this space set the values of the 5 3-pin sync switches and then an
+ RFS enable bit. The 2 additional registers trigger a init sequence for
+ the expander peripheral and configuring the I/O with the contents of
+ the value registers both with a series of I2C commands.
+
+
+
+
+ This is not a register spaces for this ctrlport interface but
+ instead register addresses on the TCA6416A. Therefore, we will just
+ define an enum with these addresses so there is no clash with the
+ above ctrlport regmap.
+
+
+
+
Value
+
Name
+
+
+
+
+
0
+
+
+
+ IO_EXP_INPUT_PORT0_REG
+
+
+
+
+
+
+
+
1
+
+
+
+ IO_EXP_INPUT_PORT1_REG
+
+
+
+
+
+
+
+
2
+
+
+
+ IO_EXP_OUTPUT_PORT0_REG
+
+
+
+
+
+
+
+
3
+
+
+
+ IO_EXP_OUTPUT_PORT1_REG
+
+
+
+
+
+
+
+
4
+
+
+
+ IO_EXP_POLARITY_INV0_REG
+
+
+
+
+
+
+
+
5
+
+
+
+ IO_EXP_POLARITY_INV1_REG
+
+
+
+
+
+
+
+
6
+
+
+
+ IO_EXP_CONFIG0_REG
+
+
+
+
+
+
+
+
7
+
+
+
+ IO_EXP_CONFIG1_REG
+
+
+
+
+
+
+ This enumerated type is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
+
+ This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
+ It uses RegType SYNC_SWITCH which is
+ defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
+
+
+
+
+ Sets I/O to control Sync Switch.
+Sets I/O state to control Sync Switch 1.
+
+ This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
+ It uses RegType SYNC_SWITCH which is
+ defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
+
+
+
+
+ Sets I/O to control Sync Switch.
+Sets I/O state to control Sync Switch 2.
+
+ This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
+ It uses RegType SYNC_SWITCH which is
+ defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
+
+
+
+
+ Sets I/O to control Sync Switch.
+Sets I/O state to control Sync Switch 3.
+
+ This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
+ It uses RegType SYNC_SWITCH which is
+ defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
+
+
+
+
+ Sets I/O to control Sync Switch.
+Sets I/O state to control Sync Switch 4.
+
+ This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
+ It uses RegType SYNC_SWITCH which is
+ defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
+
+
+
+
+ Sets I/O to control Sync Switch.
+Sets I/O state to control Sync Switch 5.
+
+ This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
+
+
+
+
+ Write to this register to trigger I/O configuration I2C sequence of
+ TCA6416A I/O expander peripheral.
+ Read from this register to check the status of reconfiguring the setup.
+
+ This window is defined in HDL source file x440_rfdc_regs.v.
+
+
+
+
+ Register space for controlling the data clock MMCM instance
+ within the RFDC block design.
+ Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the
+ regiter space description in chapter 2.
+ (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)
+
+ This register is defined in HDL source file x440_rfdc_regs.v.
+ It uses RegType RF_RESET_CONTROL_REGTYPE which is
+ defined in HDL source file common_regs.v.
+
+
+
+
+ Control register for the RF reset controller.
+ Verify the FSM ID before polling starting any reset sequence.
+ To use the SW reset triggers: Wait until DB*_DONE is de-asserted.
+ Assert either the *_RESET or *_ENABLE bitfields.
+ Wait until DB*_DONE is asserted to release the trigger.
+ The DB*_DONE signal should then de-assert.
+ Note: The *_DB1 constants are not used in the HDL, their purpose is
+ merely for documentation.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..10
+
+
Reserved
+
+
+
+
+
+
9
+
+
DAC_ENABLE
+
Write a '1' to this bit to trigger the enable sequence for
+ the daughterboard 0 DAC chain. Write a '0' once
+ db0_dac_seq_done is asserted.
+
+
+
+
+
8
+
+
DAC_RESET
+
Write a '1' to this bit to trigger a reset for the
+ daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done
+ is asserted.
+
+
+
+
+
7..6
+
+
Reserved
+
+
+
+
+
+
5
+
+
ADC_ENABLE
+
Write a '1' to this bit to trigger the enable sequence for
+ the daughterboard 0 ADC chain. Write a '0' once
+ db0_adc_seq_done is asserted.
+
+
+
+
+
4
+
+
ADC_RESET
+
Write a '1' to this bit to trigger a reset for the
+ daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done
+ is asserted.
+
+
+
+
+
3..1
+
+
Reserved
+
+
+
+
+
+
0
+
+
FSM_RESET
+
Write a '1' to this bit to reset the RF reset controller.
+ Write a '0' once db0_fsm_reset_done asserts.
+ This register is defined in HDL source file x440_rfdc_regs.v.
+ It uses RegType RF_RESET_STATUS_REGTYPE which is
+ defined in HDL source file common_regs.v.
+
+
+
+
+ Status register for the RF reset controller.
+ Verify the FSM ID before polling starting any reset sequence.
+ Refer to RF*_RESET_CONTROL_REG for instructions on how to use
+ the status bits in this register.
+ Note: The *_DB1 constants are not used in the HDL, their purpose is
+ merely for documentation.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..12
+
+
Reserved
+
+
+
+
+
+
11
+
+
DAC_SEQ_DONE
+
This bit asserts ('1') when the DB0 DAC chain reset sequence
+ is completed. The bitfield deasserts ('0') after
+ deasserting the issued triggered (enable or reset).
+
+
+
+
+
10..8
+
+
Reserved
+
+
+
+
+
+
7
+
+
ADC_SEQ_DONE
+
This bit asserts ('1') when the DB0 ADC chain reset sequence
+ is completed. The bitfield deasserts ('0') after
+ deasserting the issued triggered (enable or reset).
+
+
+
+
+
6..4
+
+
Reserved
+
+
+
+
+
+
3
+
+
FSM_RESET_DONE
+
This bit asserts ('1') when the DB0 RF reset controller FSM
+ reset sequence is completed. The bitfield deasserts ('0')
+ after deasserting db0_fsm_reset.
+ This register is defined in HDL source file x440_rfdc_regs.v.
+ It uses RegType RF_RESET_CONTROL_REGTYPE which is
+ defined in HDL source file common_regs.v.
+
+
+
+
+ Control register for the RF reset controller.
+ Verify the FSM ID before polling starting any reset sequence.
+ To use the SW reset triggers: Wait until DB*_DONE is de-asserted.
+ Assert either the *_RESET or *_ENABLE bitfields.
+ Wait until DB*_DONE is asserted to release the trigger.
+ The DB*_DONE signal should then de-assert.
+ Note: The *_DB1 constants are not used in the HDL, their purpose is
+ merely for documentation.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..10
+
+
Reserved
+
+
+
+
+
+
9
+
+
DAC_ENABLE
+
Write a '1' to this bit to trigger the enable sequence for
+ the daughterboard 0 DAC chain. Write a '0' once
+ db0_dac_seq_done is asserted.
+
+
+
+
+
8
+
+
DAC_RESET
+
Write a '1' to this bit to trigger a reset for the
+ daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done
+ is asserted.
+
+
+
+
+
7..6
+
+
Reserved
+
+
+
+
+
+
5
+
+
ADC_ENABLE
+
Write a '1' to this bit to trigger the enable sequence for
+ the daughterboard 0 ADC chain. Write a '0' once
+ db0_adc_seq_done is asserted.
+
+
+
+
+
4
+
+
ADC_RESET
+
Write a '1' to this bit to trigger a reset for the
+ daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done
+ is asserted.
+
+
+
+
+
3..1
+
+
Reserved
+
+
+
+
+
+
0
+
+
FSM_RESET
+
Write a '1' to this bit to reset the RF reset controller.
+ Write a '0' once db0_fsm_reset_done asserts.
+ This register is defined in HDL source file x440_rfdc_regs.v.
+ It uses RegType RF_RESET_STATUS_REGTYPE which is
+ defined in HDL source file common_regs.v.
+
+
+
+
+ Status register for the RF reset controller.
+ Verify the FSM ID before polling starting any reset sequence.
+ Refer to RF*_RESET_CONTROL_REG for instructions on how to use
+ the status bits in this register.
+ Note: The *_DB1 constants are not used in the HDL, their purpose is
+ merely for documentation.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..12
+
+
Reserved
+
+
+
+
+
+
11
+
+
DAC_SEQ_DONE
+
This bit asserts ('1') when the DB0 DAC chain reset sequence
+ is completed. The bitfield deasserts ('0') after
+ deasserting the issued triggered (enable or reset).
+
+
+
+
+
10..8
+
+
Reserved
+
+
+
+
+
+
7
+
+
ADC_SEQ_DONE
+
This bit asserts ('1') when the DB0 ADC chain reset sequence
+ is completed. The bitfield deasserts ('0') after
+ deasserting the issued triggered (enable or reset).
+
+
+
+
+
6..4
+
+
Reserved
+
+
+
+
+
+
3
+
+
FSM_RESET_DONE
+
This bit asserts ('1') when the DB0 RF reset controller FSM
+ reset sequence is completed. The bitfield deasserts ('0')
+ after deasserting db0_fsm_reset.
+ This register is defined in HDL source file x440_rfdc_regs.v.
+ It uses RegType RF_AXI_STATUS_REGTYPE which is
+ defined in HDL source file common_regs.v.
+
+
+
+
+ Status register for the RF AXI-Stream interfaces.
+ Note: The *_DB1 constants are not used in the HDL, their purpose is
+ merely for documentation.
+
+
+
+
Bits
Name
+
+
+
+
31..30
+
+
USER_ADC_TREADY_DB1
+
This bitfield is wired to the user's ADC (DB1) AXI-Stream
+ TReady handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
29..28
+
+
USER_ADC_TVALID_DB1
+
This bitfield is wired to the user's ADC (DB1) AXI-Stream
+ TValid handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
27..26
+
+
RFDC_ADC_I_TVALID_DB1
+
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
+ TValid handshake signals (I portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
25..24
+
+
RFDC_ADC_Q_TVALID_DB1
+
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
+ TValid handshake signals (Q portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
23..22
+
+
RFDC_ADC_I_TREADY_DB1
+
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
+ TReady handshake signals (I portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
21..20
+
+
RFDC_ADC_Q_TREADY_DB1
+
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
+ TReady handshake signals (Q portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
19..18
+
+
RFDC_DAC_TVALID_DB1
+
This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
+ TValid handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
17..16
+
+
RFDC_DAC_TREADY_DB1
+
This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
+ TReady handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
15..14
+
+
USER_ADC_TREADY
+
This bitfield is wired to the user's ADC (DB0) AXI-Stream
+ TReady handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
13..12
+
+
USER_ADC_TVALID
+
This bitfield is wired to the user's ADC (DB0) AXI-Stream
+ TValid handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
11..10
+
+
RFDC_ADC_I_TVALID
+
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
+ TValid handshake signals (I portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
9..8
+
+
RFDC_ADC_Q_TVALID
+
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
+ TValid handshake signals (Q portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
7..6
+
+
RFDC_ADC_I_TREADY
+
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
+ TReady handshake signals (I portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
5..4
+
+
RFDC_ADC_Q_TREADY
+
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
+ TReady handshake signals (Q portion). The LSB is channel 0
+ and the MSB is channel 1.
+
+
+
+
+
3..2
+
+
RFDC_DAC_TVALID
+
This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
+ TValid handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+
+
+
+
+
1..0
+
+
RFDC_DAC_TREADY
+
This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
+ TReady handshake signals. The LSB is channel 0 and the MSB
+ is channel 1.
+ This register is defined in HDL source file x440_rfdc_regs.v.
+ It uses RegType FABRIC_DSP_REGTYPE which is
+ defined in HDL source file common_regs.v.
+
+
+
+
+ This register provides information to the driver on the type
+ of DSP that is instantiated in the fabric.
+ The X410 platform supports multiple RF daughterboards, each requiring
+ a different fabric RF DSP chain that works with specific RFDC settings.
+ Each bandwidth DSP chain has a unique identifier (BW in MHz), this
+ information is conveyed in this register to let the driver
+ configure the RFDC with the proper settings.
+ Also, channel count for the DSP module is included.
+ Note: The *_DB1 constants are not used in the HDL, their purpose is
+ merely for documentation.
+
+
+
+
Bits
Name
+
+
+
+
31..20
+
+
FABRIC_DSP_BW (initialvalue=FABRIC_DSP_BW_NONE)
+
Fabric DSP BW in MHz for both daughterboards.
+
+
+
+ The values for this bitfield are in the FABRIC_DSP_BW_ENUM table.
+ (show herehide)
+
+
+
+
+
+
+
+
+
Value
+
Name
+
+
+
Dec
+
Hex
+
+
+
+
+
0
+
0x000
+
+
+
+ FABRIC_DSP_BW_NONE
+
+
+
+
+
+
+
+
100
+
0x064
+
+
+
+ FABRIC_DSP_BW_100M
+
+
+
+
+
+
+
+
200
+
0x0C8
+
+
+
+ FABRIC_DSP_BW_200M
+
+
+
+
+
+
+
+
400
+
0x190
+
+
+
+ FABRIC_DSP_BW_400M
+
+
+
+
+
+
+
+
1000
+
0x3E8
+
+
+
+ FABRIC_DSP_BW_FULL
+
+
+
+
+
+
+ This enumerated type is defined in HDL source file common_regs.v.
+
+ This register is defined in HDL source file x440_rfdc_regs.v.
+
+
+
+
+ This register enables calibration data in the DAC data path for each of the
+ four channels. Each of these bits is normally '0'. When written '1', DAC data
+ for the corresponding channel will be constantly driven with the contents of
+ the CALIBRATION_DATA register.
+
+ This register is defined in HDL source file x440_rfdc_regs.v.
+
+
+
+
+ This register shows threshold status for the ADCs. Each bit reflects the
+ RFDC's real-time ADC status signals, which will assert when the ADC input
+ signal exceeds the programmed threshold value. The status will remain
+ asserted until cleared by software.
+ The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is
+ the location of the tile in the converter column and ZZ is either 01 (the
+ lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
+ See also the Xilinx document PG269.
+
+ This register is defined in HDL source file x440_rfdc_regs.v.
+ It uses RegType RFDC_INFO_MEMTYPE which is
+ defined in HDL source file rfdc_info_pkg.sv.
+
+
+
+
+ This register provides information for one ADC/DAC within the RFSoC and its RFDC
+ configuration. There is further information on the RFNoC index of this channel.
+ The register is defined as a SystemVerilog typedef and consumed by MPM using the RFDC
+ Python register interface.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..12
+
+
Reserved
+
+
+
+
+
+
11
+
+
IS_ADC
+
If the converter is an ADC this bit is set. Otherwise it is an DAC.
+
+
+
+
+
10
+
+
DB
+
DB index.
+
+
+
+
+
9..8
+
+
CHANNEL
+
Index of the RFNoC channel per DB.
+
+
+
+
+
7..6
+
+
RESERVED2
+
Reserved for later use.
+
+
+
+
+
5..4
+
+
TILE
+
Zero based tile offset of the FPGA.
+ For DAC index i equals to FPGA tile 228+i.
+ For ADC index i equals to FPGA tile 224+i.
+
+
+
+
+
3..2
+
+
BLOCK
+
Index of the ADC/DAC within the FPGA tile.
+
+
+
+
+
1..0
+
+
BLOCK_MODE
+
The state of this ADC/DAC.
+
+
+
+ The values for this bitfield are in the RFDC_BLOCK_INFO_ENUM table.
+ (show herehide)
+
+
+
+
+
+
+
+
+
Value
+
Name
+
+
+
Dec
+
Hex
+
+
+
+
+
0
+
0x0
+
+
+
+ ENABLED
+
+
+
+
+
+
+
+
3
+
0x3
+
+
+
+ DISABLED
+
+
+
+
+
+
+ This enumerated type is defined in HDL source file rfdc_info_pkg.sv.
+
+ This register is defined in HDL source file x440_rfdc_regs.v.
+ It uses RegType RFDC_INFO_REGTYPE which is
+ defined in HDL source file common_regs.v.
+
+
+
+
+ This register provides information about how the RFDC is connected to
+ the rest of the fabric.
+ Specifically, between the actual RFDC and the RFNoC infrastructure,
+ there may be additional resampling (if the RFDC resampler cannot handle
+ all the resampling itself) and it is important to know how wide the
+ connection from the RFDC gearbox FIFO to the rest of the design is.
+ Note: The *_DB1 constants are not used in the HDL, their purpose is
+ merely for documentation.
+
+
+
+
Bits
Name
+
+
+
+
31..26
+
+
Reserved
+
+
+
+
+
+
25..23
+
+
RFDC_INFO_SPC_TX_DB1 (initialvalue=1)
+
Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 1.
+
+
+
+
+
22..20
+
+
RFDC_INFO_SPC_RX_DB1 (initialvalue=1)
+
Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 1.
+
+
+
+
+
19..16
+
+
RFDC_INFO_XTRA_RESAMP_DB1 (initialvalue=1)
+
Additional resampling happening outside the RFDC for daughterboard 0.
+
+
+
+
+
15..10
+
+
Reserved
+
+
+
+
+
+
9..7
+
+
RFDC_INFO_SPC_TX (initialvalue=1)
+
Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 0.
+
+
+
+
+
6..4
+
+
RFDC_INFO_SPC_RX (initialvalue=1)
+
Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 0.
+
+
+
+
+
3..0
+
+
RFDC_INFO_XTRA_RESAMP (initialvalue=1)
+
Additional resampling happening outside the RFDC for daughterboard 0.
+ This register is defined in HDL source file rfdc_timing_control.v.
+
+
+
+
+ Gearbox reset control register.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
Reserved
+
+
+
+
+
+
23..16
+
+
Reserved
+
+
+
+
+
+
15..8
+
+
Reserved
+
+
+
+
+
+
7..2
+
+
Reserved
+
+
+
+
+
+
1w
+
+
DAC_RESET (Strobe)
+
This reset is for the gearbox on the DAC data path that is used to
+ move data from one clock domain to another outside the RFDC. Write
+ a 1 to this bit to send a reset pulse to the DAC gearbox.
+
+
+
+
+
0w
+
+
ADC_RESET (Strobe)
+
This reset is for the gearbox on the ADC data path that is used to
+ move data from one clock domain to another outside the RFDC. Write
+ a 1 to this bit to send a reset pulse to the ADC gearbox.
For information about the register content and the way to interact with the core see the
+documentation
+of the SPI master from opencores used internally.
+
The core is configured to operate with 16 slave signal signals, up to 128 bits per transmission and 8 bit clock divider.
+Only 64 bits of data are available via this register interface.
+
For the different SPI modes use the following table to derive the bits in CONTROL register. Only option 0 (CPOL=0, CPHA=0) has been tested.
+ This register is defined in HDL source file uhd_regs.v.
+
+
+
+
+
+
+
+
+
+
Bits
Name
+
+
+
+
31..16
+
+
pause_clear
+
+
If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause.
+Pause clear must be less than pause set or terrible things will happen.
+The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only
+used with 100Gb ethernet
+
+
+
+
+
15..0
+
+
pause_set
+
+
If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only
+used with 100Gb ethernet
+ Daughterboard GPIO interface.
+ For guidance on when to update these revision numbers,
+ please refer to the register map documentation accordingly:
+
+ This enum contains indexes for all the components in the X410
+ (both common and app-specific) which version information is
+ desired to be available for compatibility tracking purposes.
+
+
Description
Index range
Max # of components
+
Common components
0 to 23
24
+
UHD-specific components
24 to 43
20
+
LV-specific components
44 to 63
20
+
+
+
+
+
Value
+
Name
+
+
+
+
+
0
+
+
+
+ FPGA_VERSION_INDEX
+
+
+
+
+
+
+
+
1
+
+
+
+ CPLD_IFC_INDEX
+
+
+
+
+
+
+
+
2
+
+
+
+ DB0_RF_CORE_INDEX
+
+
+
+
+
+
+
+
3
+
+
+
+ DB1_RF_CORE_INDEX
+
+
+
+
+
+
+
+
4
+
+
+
+ DB0_GPIO_IFC_INDEX
+
+
+
+
+
+
+
+
5
+
+
+
+ DB1_GPIO_IFC_INDEX
+
+
+
+
+
+
+ This enumerated type is defined in HDL source file x4xx_versioning_regs.v.
+
+ This register is defined in HDL source file x4xx_versioning_regs.v.
+ It uses RegType VERSION_TYPE which is
+ defined in HDL source file x4xx_versioning_regs.v.
+
+
+
+
+ Component's current version.
+ This register contains the current component's version implemented in HDL.
+ The current version shall be used to detect a component being too
+ old for the driver/software:
+ SW oldest compatible version > Component's current version --> Component is too old.
+
+
+
+
Bits
Name
+
+
+
+
31..23
+
+
MAJOR (initialvalue=0)
+
Major number (max = 511): an increase reflects a breaking change.
+ IMPORTANT!MAJOR must always remain in sync between the component's
+ CURRENT_VERSION and OLDEST_COMPATIBLE_VERSION registers.
a new feature is added to the component, which does not conflict with the driver.
+
minor implementation changes were made to the component which are worth tracking.
+
the component has added new bitfields/registers that do not require software interaction
+ (i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to
+ previously undefined bits).
+
Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
+ but that should not impact the component's behavior
+ Eventually, this number is intended to be automatically incremented for any new build.
+ This register is defined in HDL source file x4xx_versioning_regs.v.
+ It uses RegType VERSION_TYPE which is
+ defined in HDL source file x4xx_versioning_regs.v.
+
+
+
+
+ Component's oldest compatible version.
+ This register contains the oldest compatible component's version, that is the oldest
+ component's implementation that is compatible with the current implementation.
+ The oldest compatible version shall be used to detect a component being too
+ new for the driver/software:
+ SW current version < Component's oldest compatible version --> Component is too new.
+
+
+
+
Bits
Name
+
+
+
+
31..23
+
+
MAJOR (initialvalue=0)
+
Major number (max = 511): an increase reflects a breaking change.
+ IMPORTANT!MAJOR must always remain in sync between the component's
+ CURRENT_VERSION and OLDEST_COMPATIBLE_VERSION registers.
a new feature is added to the component, which does not conflict with the driver.
+
minor implementation changes were made to the component which are worth tracking.
+
the component has added new bitfields/registers that do not require software interaction
+ (i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to
+ previously undefined bits).
+
Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
+ but that should not impact the component's behavior
+ Eventually, this number is intended to be automatically incremented for any new build.
+ This register is defined in HDL source file x4xx_versioning_regs.v.
+ It uses RegType TIMESTAMP_TYPE which is
+ defined in HDL source file x4xx_versioning_regs.v.
+
+
+
+
+ Component's versions update time.
+ This register provides the time stamp for the last modification to
+ the component's versions (current & oldest compatible).
+ The time stamp is provided in hexadecimal format: 0xYYMMDDHH.
+
+
+
+
Bits
Name
+
+
+
+
31..24
+
+
YY
+
This is the year number after 2000 (e.g. 2019 = 0x19).
+ This register is defined in HDL source file x4xx_versioning_regs.v.
+ It uses RegType RESERVED_TYPE which is
+ defined in HDL source file x4xx_versioning_regs.v.
+
- This section lists all common Processing System ports through
- which the register maps in this project are accessed. Each input
- port to the fabric will point to a regmap.
-
-
-This is the main AXI4-Lite master interface that the PS
- exposes to the kernel to interact with the FPGA fabric.
- There are multiple endpoints connected to this interface.
-
-
-
-
- This port is defined in HDL source file x440_rfdc_regs.v.
-
-
-This is the SPI1 interface
- (see Zynq UltraScale+ Devices Register Reference)
- of the PS.
- With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.
- The request format on SPI is defined as.
- Write request:
-
-
1'b1 = write
-
15 bit address
-
32 bit data (MOSI)
-
8 bit processing gap
-
5 bit padding
-
1 bit ack
-
2 bit status
-
- Read request:
-
-
1'b0 = read
-
15 bit address
-
8 bit processing gap
-
32 bit data (MISO)
-
5 bit padding
-
1 bit ack
-
2 bit status
-
-
-
-
-
- This port is defined in HDL source file x440_rfdc_regs.v.
-
-
-
-
-
-
-
-
-
-
-
AXI_HPM0_REGMAP
-
-
This is the map for the register space that the Processing System's
-M_AXI_HPM0_FPD port (AXI4 master interface) has access to.
-This port has a 40-bit address bus.
- Basic registers containing version and capabilities information.
-
-
-
-
CONSTANTS_ENUM Enumeration
-This enumeration is used to create the constants held in the basic registers.
-
-
-
-
Value
-
Name
-
-
-
-
-
-
Dec
-
-
Hex
-
-
-
-
-
-
173157672
-
-
0x0A522D28
-
-
-
PS_CPLD_SIGNATURE
-
-
-
-
-
-
-
-
570950676
-
-
0x22080414
-
-
-
CPLD_REVISION
-
-
-
-
-
-
-
-
570950676
-
-
0x22080414
-
-
-
OLDEST_CPLD_REVISION
-
-
-
-
-
-
-
-
1071406151
-
-
0x3FDC5C47
-
-
-
PL_CPLD_SIGNATURE
-
-
-
-
-
-
-
-
- This enumerated type is defined in HDL source file mb_cpld.v.
-
-
-
-
-
-
-
-
-
-
-
CORE_REGS_REGMAP
- This is the map for the registers that the CORE_REGS window has access to
- from the ARM_AXI_HPM0_FPD port.
-
- The registers contained here conform the mboard-regs node that MPM uses
- to manage general FPGA control/status calls, such as versioning,
- timekeeper, GPIO, etc.
-
- The following diagram shows how the communication bus interacts with the
- modules in CORE_REGS.
-
This register is defined in HDL source file cpld_interface_regs.v.
-
-
-
-
-
-Read/write register for general software use.
-
-
-
-
-
-
-
-
CPLD_SPI_CONTROL_REGS
- Registers to control the SPI clock frequency of the CPLD interfaces.
- The resulting clock frequency is calculated by .
-
- Note that the PLL Reference Clock (PRC) is depending on the RF clocks.
-
This register is defined in HDL source file cpld_interface_regs.v.
-
-
-
-
-
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..8
-
-
Reserved
-
-
-
-
-
-
-
7..1
-
-
Reserved
-
-
-
-
-
-
-
0
-
-
IPASS_ENABLE_TRANSFER
-
If 1 enables the forwarding of iPass cable present signal to MB CPLD
- using ctrlport requests. On change from 0 to 1 the current status is
- transferred to the MB CPLD via SPI ctrlport request initially.
This register is defined in HDL source file x4xx_gpio_spi.v.
-
-
-
-
-
-Starts a SPI transaction
-
-
-
-
-
Bits
Name
-
-
-
31..0w
-
-
SPI_DATA (initialvalue=0)
-
Payload to be sent for the SPI transaction. If the payload is shorter than 32 bits,
- it must be aligned to the MSbs in this field. LSbs are ignored in this scenario.
This register is defined in HDL source file x4xx_gpio_spi.v.
-
-
-
-
-
-Contains information pertaining this SPI controller block.
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..8
-
-
Reserved
-
-
-
-
-
-
-
7..4
-
-
Reserved
-
-
-
-
-
-
-
3..0
-
-
SLAVE_COUNT
-
Indicates the number SPI slaves configurable by the controller.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DIO_REGMAP
-
-
DIO_REGS
- Registers to control the GPIO buffer direction on the FPGA connected to
- the DIO board. Further registers enable different sources to control and
- read the GPIO lines as master. The following diagram shows how source
- selection multiplexers are arranged, as well as an indicator for the
- register that control them.
-
- Make sure the GPIO lines between FPGA and GPIO board are not driven by
- two drivers. Set the DIO registers in PS_CPLD_BASE_REGMAP appropriately.
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Sets whether the DIO signal line is driven by this register interface
- or the user application.
- 0 = user application is master, 1 = output of SW_DIO_CONTROL is master
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Set the direction of FPGA buffer connected to DIO ports on the DIO board.
- Each bit represents one signal line. 0 = line is an input to the FPGA,
- 1 = line is an output driven by the FPGA.
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Controls the values on each DIO signal line in case the line master is
- set to PS in DIO_MASTER_REGISTER.
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Controls whether the DIO lines reflect the state of DIO_MASTER_REGISTER
- or the radio blocks. 0 = DIO_MASTER_REGISTER,
- 1 = Radio block output(DIO_OVERRIDE)
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Controls which radio block to use the ATR state from to determine the
- state of the DIO lines.
- 0 = Radio#0
- 1 = Radio#1
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Controls which of the two available digital interfaces controls the DIO lines.
- 0 = Digital interface from Radio#0,
- 1 = Digital Interface from Radio#1.
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Controls whether the radio input to the DIO_SOURCE_REGISTER mux
- connects to the ATR control or a Digital interface block. The output
- of the mux controlled by this bit goes to DIO_SOURCE_REGISTER.
- 0 = Drive the ATR state(RADIO_SOURCE_REGISTER), 1 = Drive
- Digital interface block(Output of INTERFACE_DIO_SELECT).
-
-
This register is defined in HDL source file x4xx_dio.v.
-It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.
-
-
-
-
-
-Holds a single bit setting for DIO lines in both ports. One bit per pin.
-Controls which source is forwarded to the DIO_MASTER_REGISTER mux.
- This configuration is applied independently for each DIO line.
- 0 = MPM Ctrlport endpoint, 1 = PS Netlist DIO signal.
-
-
-
-
-
Bits
Name
-
-
-
31..28
-
-
Reserved
-
-
-
-
-
-
-
27..16
-
-
DIO_PORT_B (initialvalue=0)
-
-
-
-
-
-
-
15..12
-
-
Reserved
-
-
-
-
-
-
-
11..0
-
-
DIO_PORT_A (initialvalue=0)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DMA_REGMAP
-
-
-
XILINX_DMA_REGISTERS
-
-
Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11
- This is the map that the nixge driver uses in Ethernet DMA to
- move data between the Processing System's architecture and the fabric.
- This map is a combination of two main components: a Xilix AXI DMA engine
- and some registers for MAC/PHY control.
-
This window is defined in HDL source file common_regs.v.
-
-
-
-
-
-Refer to Xilinx' AXI DMA v7.1 IP product guide for further
- information on this register map:
- https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
-
-
This register is defined in HDL source file x4xx_global_regs.v.
-
-
-
-
-
-Control register for clocking resources.
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
PPS_BRC_DELAY
-
Number of base reference clock cycles from appearance of the PPS
- rising edge to the occurrence of the aligned edge of base reference
- clock and PLL reference clock at the sample PLL output. This number
- is the sum of the actual value based on PLL_SYNC_DELAY (also
- accumulate the fixed amount of clock cycles) and if any the number of
- cycles the SPLL requires from issuing of the SYNC signal to the
- aligned edge (with LMK04832 = 0).
- The number written to this register has to be reduced by 1 due to
- HDL implementation.
-
-
-
-
-
-
23..16
-
-
PLL_SYNC_DELAY
-
Due to the HDL implementation the rising edge of the SYNC signal for
- the LMK04832 is generated 2 clock cycles after the PPS rising edge.
- This delay can be further increased by setting this delay value
- (e.g. PLL_SYNC_DELAY=3 will result in a total delay of 5 clock cycles).
- In case two X400 devices are connected using the PPS and reference clock the master delay value needs to be 3 clock cycles
- higher than the slave delay value to align the LMK sync edges in time.
Assertion triggers the SYNC signal generation for LMK04832 after the next appearance of the PPS rising edge.
- There is no self reset on this trigger.
- Keep this trigger asserted until PLL_SYNC_DONE is asserted.
-
-
-
-
-
-
7..6
-
-
Reserved
-
-
-
-
-
-
-
5..4
-
-
TRIGGER_IO_SELECT (initialvalue=TRIG_IO_INPUT)
-
IMPORTANT! SW must ensure any TRIG_IO consumers (downstream devices) ignore
- and/or re-sync after enabling this port, since the output-enable is basically
- asynchronous to the actual TRIG_IO driver.
-
-
- The values for this bitfield are in the TRIG_IO_ENUM table.
- (show here)
-
-
-
-
-
-
-
-
-
-
Value
-
Name
-
-
-
-
-
-
0
-
-
-
TRIG_IO_INPUT
-
-
-
-
-
-
-
-
1
-
-
-
TRIG_IO_PPS_OUTPUT
-
-
-
-
-
-
-
-
- This enumerated type is defined in HDL source file x4xx_global_regs.v.
-
-
-
-
-
-
-
-
-
-
-
3r
-
-
REFCLK_LOCKED
-
RESERVED. This bit is not implemented on X4xx and reads as 0.
-
-
-
-
-
-
2
-
-
REF_SELECT
-
RESERVED. This bit is not implemented on X4xx and reads as 0.
-
-
-
-
-
-
1..0
-
-
PPS_SELECT (initialvalue=PPS_INT_25MHZ)
-
Select the source of the PPS signal.
- For the internal generation the value depending on the base reference clock has to be chosen.
- The external reference is taken from the PPS_IN pin and is independent of the base reference clock.
-
-
- The values for this bitfield are in the PPS_ENUM table.
- (show here)
-
-
-
-
-
-
-
-
-
-
Value
-
Name
-
-
-
-
-
-
0
-
-
-
PPS_INT_25MHZ
-
-
-
-
-
-
-
-
1
-
-
-
PPS_INT_10MHZ
-
-
-
-
-
-
-
-
2
-
-
-
PPS_EXT
-
-
-
-
-
-
-
-
- This enumerated type is defined in HDL source file x4xx_global_regs.v.
-
This register is defined in HDL source file x4xx_global_regs.v.
-
-
-
-
-
-Control registers for PPS generation.
-
-
-
-
-
Bits
Name
-
-
-
31
-
-
PPS_RC_ENABLED
-
Enables the PPS signal in radio clock domain. Please make sure that
- the values of PPS_BRC_DELAY, PPS_PRC_DELAY, PRC_RC0_DIVIDER and
- PRC_RC1_DIVIDER are set before enabling this bit. It is recommended
- to disable the PPS for changes on the other values. Use a wait time of
- at least 1 second before changing this value to ensure the values are
- stable for the next PPS edge.
-
-
-
-
-
-
30..26
-
-
Reserved
-
-
-
-
-
-
-
25..0
-
-
PPS_PRC_DELAY
-
The number of PLL reference clock cycles from one aligned edge to the
- desired aligned edge to issue the PPS in radio clock domain. This
- delay is configurable to any aligned edge within a maximum delay of 1
- second (period of PPS).
- The value written to the register has to be reduced by 5 due to
- HDL implementation.
This register is defined in HDL source file x4xx_global_regs.v.
-
-
-
-
-
-Build seed used for this compilation. Making this value readable
- ensures that compilation results are affected by the value in this
- register.
-
-
This register is defined in HDL source file x4xx_global_regs.v.
-
-
-
-
-
-Control registers for PPS clock crossing to the radio clock domain.
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..21
-
-
Reserved
-
-
-
-
-
-
-
20..16
-
-
PRC_RC1_DIVIDER
-
Clock multiplier used to generate radio clock 1 from PLL reference clock.
- The value written to the register has to follow the following formula:
- PRC_RC1_DIVIDER = (RADIO_CLK_1 / PRC_CLK) * 2 - 2
-
-
-
-
-
-
15..8
-
-
Reserved
-
-
-
-
-
-
-
7..5
-
-
Reserved
-
-
-
-
-
-
-
4..0
-
-
PRC_RC0_DIVIDER
-
Clock multiplier used to generate radio clock 0 from PLL reference clock.
- The value written to the register has to follow the following formula:
- PRC_RC0_DIVIDER = (RADIO_CLK_0 / PRC_CLK) * 2 - 2
This register is defined in HDL source file x4xx_global_regs.v.
-
-
-
-
-
-Status register for mfg_test functions.
-
-
-
-
-
Bits
Name
-
-
-
31..26
-
-
Reserved
-
-
-
-
-
-
-
25..0
-
-
MFG_TEST_FPGA_AUX_REF_FREQ
-
Report the time between rising edges on the FPGA_REF_CLK
- input port in 40 MHz Clock ticks. If the count extends
- to 1.2 seconds without an edge, the value reported is set
- to zero.
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x00C000 + i*4
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file x4xx_gpio_atr.v.
-It uses RegType GPIO_ATR_STATE which is defined in HDL source file x4xx_gpio_atr.v.
-
-
-
-
-
-Holds a single bit setting for GPIO lines in both ports for a particular ATR sate
-Describes GPIO behavior for the different ATR states. When ATR_OPTION
- is set to use the DB states, TX and RX states for RF0 and RF1 are
- combined to create a single vector. This creates 16 different
- combinations, each with its own register. When ATR_OPTION is set to
- classic ATR, offsets 0x00-0x03 in this register group will be driven
- in accordance with the state of RF0, and offsets 0x04-0x07 will be
- driven in accordance with the state of RF1.
- CLASSIC ATR MAPPING: Idle[RF0:0x00; RF1:0x04], RX[RF0:0x01; RF1:0x05],
- TX[RF0:0x02; RF1:0x06], FDX[RF0:0x03; RF1:0x07]
-
-
This register is defined in HDL source file x4xx_gpio_atr.v.
-
-
-
-
-
-Controls the RF state mapping of each GPIO line when classic
- ATR mode is active.
-
-
-
-
-
Bits
Name
-
-
-
31..28
-
-
Reserved
-
-
-
-
-
-
-
27..16
-
-
RF_SELECT_B (initialvalue=0)
-
Set which RF channel's state to reflect in the pins of
- HDMI connector B when ATR_OPTION is set to classic ATR.
- Controlled in a per-pin basis.
- 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03)
- 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)
-
-
-
-
-
-
15..12
-
-
Reserved
-
-
-
-
-
-
-
11..0
-
-
RF_SELECT_A (initialvalue=0)
-
Set which RF channel's state to reflect in the pins for
- HDMI connector A when ATR_OPTION is set to classic ATR.
- Controlled in a per-pin basis.
- 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03)
- 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)
This register is defined in HDL source file x4xx_gpio_atr.v.
-
-
-
-
-
-Controls whether GPIO lines use the TX and RX state of an RF channel
- (Classic ATR) or the daughterboard state the selector for the
- ATR_STATE.
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..8
-
-
Reserved
-
-
-
-
-
-
-
7..1
-
-
Reserved
-
-
-
-
-
-
-
0
-
-
ATR_OPTION (initialvalue=0)
-
Sets the scheme in which RF states in the radio will control GPIO
- lines. 0 = DB state is used. RF states are combined and the
- GPIO state is driven based on all 16 ATR_STATE registers.
- 1 = Each RF channel has its separate ATR state(Classic ATR).
- Use register CLASSIC_ATR_CONFIG to indicate the RF channel
- to which each GPIO line responds to.
This register is defined in HDL source file x4xx_gpio_atr.v.
-
-
-
-
-
-Reflects the logic state of each GPIO input.
-
-
-
-
-
Bits
Name
-
-
-
31..28
-
-
Reserved
-
-
-
-
-
-
-
27..16
-
-
GPIO_IN_B (initialvalue=0)
-
-
-
-
-
-
-
15..12
-
-
Reserved
-
-
-
-
-
-
-
11..0
-
-
GPIO_IN_A (initialvalue=0)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LED_ATR_REGMAP
-
-
LED_ATR_REGISTERS
- Each channel in the FBX daughterboard has 3 LEDs. TXRX Red/Green LEDs and RX2 Green LED.
- This register map describes how to control the behavior of the 3 LEDs.
- There are three supported control schemes for these LEDs:
-
-
ATR Disabled - Single persistent state.
-
Classic ATR - Each channel's LEDs depend on the transmission state
- of the respective channel.
-
DB State - Each channel's LEDs depend on the transmission state
- of all channels in this radio.
-
-
-
-
-
LED_SIZE_TYPE Enumeration
-
-
-
-
-
Value
-
Name
-
-
-
-
-
-
3
-
-
-
LED_SIZE
-
-
-
-
-
-
-
-
- This enumerated type is defined in HDL source file led_atr_control.v.
-
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x004000 + i*4
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file led_atr_control.v.
-It uses RegType LED_ATR_STATE which is defined in HDL source file led_atr_control.v.
-
-
-
-
-
-Holds the value for the control lines of each channel's LEDs
- for a particular ATR sate
-Describes led behavior for the different ATR states. When LED0_ATR_OPTION
- is set to use the DB states, TX and RX states for LED0-LED3 are
- combined to create a single vector. This creates 256 different
- combinations, each with its own register. When LED0_ATR_OPTION is set to
- classic ATR, the first 4 offsets in this register group will be driven
- in accordance with the state of RF0.
- CLASSIC ATR MAPPING: Idle[RF0: TX=0, RX=0], RX[RF0: TX=0, RX=1,
- TX[RF0: TX=1, RX=0], FDX[RF0: TX=1, RX=1]
-
-
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x004400 + i*4
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file led_atr_control.v.
-It uses RegType LED_ATR_STATE which is defined in HDL source file led_atr_control.v.
-
-
-
-
-
-Holds the value for the control lines of each channel's LEDs
- for a particular ATR sate
-Describes led behavior for the different ATR states. When LED1_ATR_OPTION
- is set to use the DB states, TX and RX states for LED0-LED3 are
- combined to create a single vector. This creates 256 different
- combinations, each with its own register. When LED1_ATR_OPTION is set to
- classic ATR, the first 4 offsets in this register group will be driven
- in accordance with the state of RF1.
- CLASSIC ATR MAPPING: Idle[RF1: TX=0, RX=0], RX[RF1: TX=0, RX=1,
- TX[RF1: TX=1, RX=0], FDX[RF1: TX=1, RX=1]
-
-
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x004800 + i*4
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file led_atr_control.v.
-It uses RegType LED_ATR_STATE which is defined in HDL source file led_atr_control.v.
-
-
-
-
-
-Holds the value for the control lines of each channel's LEDs
- for a particular ATR sate
-Describes led behavior for the different ATR states. When LED2_ATR_OPTION
- is set to use the DB states, TX and RX states for LED0-LED3 are
- combined to create a single vector. This creates 256 different
- combinations, each with its own register. When LED2_ATR_OPTION is set to
- classic ATR, the first 4 offsets in this register group will be driven
- in accordance with the state of RF2.
- CLASSIC ATR MAPPING: Idle[RF2: TX=0, RX=0], RX[RF2: TX=0, RX=1,
- TX[RF2: TX=1, RX=0], FDX[RF2: TX=1, RX=1]
-
-
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x004C00 + i*4
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file led_atr_control.v.
-It uses RegType LED_ATR_STATE which is defined in HDL source file led_atr_control.v.
-
-
-
-
-
-Holds the value for the control lines of each channel's LEDs
- for a particular ATR sate
-Describes led behavior for the different ATR states. When LED3_ATR_OPTION
- is set to use the DB states, TX and RX states for LED0-LED3 are
- combined to create a single vector. This creates 256 different
- combinations, each with its own register. When LED3_ATR_OPTION is set to
- classic ATR, the first 4 offsets in this register group will be driven
- in accordance with the state of RF3.
- CLASSIC ATR MAPPING: Idle[RF3: TX=0, RX=0], RX[RF3: TX=0, RX=1,
- TX[RF3: TX=1, RX=0], FDX[RF3: TX=1, RX=1]
-
-
This register is defined in HDL source file led_atr_control.v.
-
-
-
-
-
-Controls whether switch control lines use the TX and RX state of
- their respective channel (Classic ATR) or the daughterboard state
- to select which state to use from values set in LED_ATR_STATE registers.
- For each particular bit:
- 0: Use DB state for ATR
- 1: Classic ATR mode.
-
-
This register is defined in HDL source file led_control.v.
-
-
-
-
-
-This register configures RF Frontend LEDs.
-
-
-
-
-
Bits
Name
-
-
-
31..27
-
-
Reserved
-
-
-
-
-
-
-
26
-
-
CH3_TRX1_LED_GR_EN (initialvalue=0)
-
Enables the Ch3 TRX (RX) Green LED
-
-
-
-
-
-
25
-
-
CH3_TRX1_LED_RED_EN (initialvalue=0)
-
Enables the Ch3 TRX (TX) Red LED
-
-
-
-
-
-
24
-
-
CH3_RX2_LED_EN (initialvalue=0)
-
Enables the Ch3 Rx2 Green LED
-
-
-
-
-
-
23..19
-
-
Reserved
-
-
-
-
-
-
-
18
-
-
CH2_TRX1_LED_GR_EN (initialvalue=0)
-
Enables the Ch2 TRX (RX) Green LED
-
-
-
-
-
-
17
-
-
CH2_TRX1_LED_RED_EN (initialvalue=0)
-
Enables the Ch2 TRX (TX) Red LED
-
-
-
-
-
-
16
-
-
CH2_RX2_LED_EN (initialvalue=0)
-
Enables the Ch2 Rx2 Green LED
-
-
-
-
-
-
15..11
-
-
Reserved
-
-
-
-
-
-
-
10
-
-
CH1_TRX1_LED_GR_EN (initialvalue=0)
-
Enables the Ch1 TRX (RX) Green LED
-
-
-
-
-
-
9
-
-
CH1_TRX1_LED_RED_EN (initialvalue=0)
-
Enables the Ch1 TRX (TX) Red LED
-
-
-
-
-
-
8
-
-
CH1_RX2_LED_EN (initialvalue=0)
-
Enables the Ch1 Rx2 Green LED
-
-
-
-
-
-
7..3
-
-
Reserved
-
-
-
-
-
-
-
2
-
-
CH0_TRX1_LED_GR_EN (initialvalue=0)
-
Enables the Ch0 TRX (RX) Green LED
-
-
-
-
-
-
1
-
-
CH0_TRX1_LED_RED_EN (initialvalue=0)
-
Enables the Ch0 TRX (TX) Red LED
-
-
-
-
-
-
0
-
-
CH0_RX2_LED_EN (initialvalue=0)
-
Enables the Ch0 Rx2 Green LED
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MB_CPLD_PL_REGMAP
-
-
This register map is available using the PL CPLD SPI interface.
-All protocol masters controller by this register map are running with a clock frequency of 50 MHz.
This register is defined in HDL source file uhd_regs.v.
-
-
-
-
-
-
-
Definition of this register depends on Protocol
-
10GBE
-
READ - Status
-
-
0 = status_crc_error
-
1 = status_fragment_error
-
2 = status_txdfifo_ovflow
-
3 = status_txdfifo_udflow
-
4 = status_rxdfifo_ovflow
-
5 = status_rxdfifo_udflow
-
6 = status_pause_frame_rx
-
7 = status_local_fault
-
8 = status_remote_fault
-
-
WRITE - Ctl
-
-
0 = ctrl_tx_enable
-
-
100 GBE
-
READ - Status
-
-
0 = tx_ovfout - Sets if TX overflow reported by CMAC
- (Stays set till MAC is reset). This is a fatal error
-
1 = tx_unfout - Sets if TX underflow reported by CMAC
- (Stays set till MAC is reset). This is a fatal error
-
2 = stat_rx_aligned - goes high when CMAC has finished
- alignment, and is ready to start reception of traffic.
-
3 = mac_dropped_packet - If the mac RX wants to push data(TVALID)
- but upstream is trying to hold(TREADY)off we drop a packet.
- Upstream circuitry should detect this when traffic is forked
- between CHDR and CPU, so this bit will only set if there is a
- HW design error.
-
4 = auto_config_done - This bit goes high when the auto_config
- state machine finishes operation. It is very similiar to
- stat_rx_alligned, but waits for extra writes which occur
- after allignement to complete.
-
24:16 = pause_mask - readable version of pause_mask bellow.
-
-
WRITE - Ctl
-
-
0 = auto_enable - Defaults to ON after reset - Enables a
- state machine that performs CMAC register writes to
- bring up the MAC without SW intervention.
-
24:16 = pause_mask - A second layer of enables(the first being
- register in the CMAC) on the pause_request mechanic. Bits
- 7:0 of enable pause on PFC7:0. Bit 8 enables global pause
- request (not priority controlled). The mask is used for TX
- and RX.
This register is defined in HDL source file pl_cpld_regs.v.
-
-
-
-
-
-Provides to the LEDs of the QSFP ports.
- Write access will directly change the LED status.
- The LED lights up if the corresponding bit is set.
-
-
This register is defined in HDL source file pl_cpld_regs.v.
-
-
-
-
-
-This register returns (in YYMMDDHH format) the oldest revision
- that is still compatible with this one. Compatible means that
- registers or register bits may have been added, but not
- modified or deleted (see OLDEST_CPLD_REVISION of CONSTANTS_REGMAP).
-
-
This register is defined in HDL source file pl_cpld_regs.v.
-
-
-
-
-
-Git hash of commit used to build this image.
- Value equals 0xDEADBEEF if the git hash was not used during synthesis.
-
-
-
-
-
Bits
Name
-
-
-
31..28
-
-
GIT_CLEAN
-
0x0 in case the git status was clean
- 0xF in case there were uncommitted changes
-
-
-
-
-
-
27..0
-
-
GIT_HASH
-
7 hex digit hash code of the commit
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PL_CPLD_REGMAP
- This register map is available from the PS via AXI and MPM endpoint.
- Its size is 128K (17 bits). Only the 17 LSBs are used as address in this documentation.
-
This window is defined in HDL source file cpld_interface.v.
-
-
-
-
-
-All registers of the second DB CPLD. Register map will be added later on.
-
-
-
-
-
-
-
-
-
-
-
-
PL_DMA_MASTER_REGMAP
- This is a regmap to document the different ports that have access to the PS system memory.
- Each port may have different restrictions on system memory. See the corresponding window
- for details
-
This window is defined in HDL source file common_regs.v.
-
-
-
-
-
-The HPC0 port of the PS is used for general purpose cache-coherent accesses
- to the PS system memory. Different applications may use it for different
- purposes. Its access is configured as follows:
-
This window is defined in HDL source file common_regs.v.
-
-
-
-
-
-The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave
- interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx.
- Its access is configured as follows:
-
-
Offset
Size
Description
-
0x000800000000
0x000800000000
DDR_HIGH
-
0x00000000
0x80000000
DDR_LOW
-
0xC0000000
0x20000000
QSPI
-
-
-
-
-
-
-
-
-
-
-
-
-
PS_CPLD_BASE_REGMAP
-
-
DIO_REGS
- Registers to control the GPIO buffer direction on the DIO board connected to the FPGA.
- Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers.
- Set the direction in the FPGA's DIO register appropriately.
-
This register is defined in HDL source file ps_cpld_regs.v.
-
-
-
-
-
-Set the direction of FPGA buffer connected to DIO ports on the DIO board.
- Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA.
-
-
This register is defined in HDL source file ps_cpld_regs.v.
-
-
-
-
-
-Register to control the PL part DB SPI connection and reset generation.
- The DB connection is clocked with PLL reference clock. Ensure this clock is stable
- and enabled before starting any SPI request.
- The PLL reference clock can be disabled if both DB connections are disabled or inactive.
- To enable the DB connection, enable clock with one write access and release
- reset with the next write access.
- To disable the DB connection, assert reset with one write access and
- disable clocks with the next write access.
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..22
-
-
Reserved
-
-
-
-
-
-
-
21w
-
-
ASSERT_RESET_DB1
-
Writing with this flag set asserts reset for DB 1 (overrides RELEASE_RESET_DB1)
-
-
-
-
-
-
20w
-
-
ASSERT_RESET_DB0
-
Writing with this flag set asserts reset for DB 0 (overrides RELEASE_RESET_DB0)
-
-
-
-
-
-
19..18
-
-
Reserved
-
-
-
-
-
-
-
17w
-
-
RELEASE_RESET_DB1
-
Writing with this flag set releases DB 1 reset. (may be overwritten by ASSERT_RESET_DB1)
-
-
-
-
-
-
16w
-
-
RELEASE_RESET_DB0
-
Writing with this flag set releases DB 0 reset. (may be overwritten by ASSERT_RESET_DB0)
-
-
-
-
-
-
15
-
-
Reserved
-
-
-
-
-
-
-
14w
-
-
DISABLE_PLL_REF_CLOCK
-
Writing with this flag set disables the PLL reference clock (overrides ENABLE_PLL_REF_CLOCK). Assert this flag to reconfigure the clock.
-
-
-
-
-
-
13w
-
-
DISABLE_CLOCK_DB1
-
Writing with this flag set disables DB 1 clock forwarding (overrides ENABLE_CLOCK_DB1)
-
-
-
-
-
-
12w
-
-
DISABLE_CLOCK_DB0
-
Writing with this flag set disables DB 0 clock forwarding (overrides ENABLE_CLOCK_DB0)
-
-
-
-
-
-
11
-
-
Reserved
-
-
-
-
-
-
-
10w
-
-
ENABLE_PLL_REF_CLOCK
-
Writing with this flag set enables the PLL reference clock. Assert this flag after PLL reference clock is stable. (may be overwritten by DISABLE_PLL_REF_CLOCK)
-
-
-
-
-
-
9w
-
-
ENABLE_CLOCK_DB1
-
Writing with this flag set enables DB 1 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB1)
-
-
-
-
-
-
8w
-
-
ENABLE_CLOCK_DB0
-
Writing with this flag set enables DB 0 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB0)
-
-
-
-
-
-
7..6
-
-
Reserved
-
-
-
-
-
-
-
5r
-
-
DB1_RESET_ASSERTED
-
Indicates that reset is asserted for DB 1.
-
-
-
-
-
-
4r
-
-
DB0_RESET_ASSERTED
-
Indicates that reset is asserted for DB 0.
-
-
-
-
-
-
3
-
-
Reserved
-
-
-
-
-
-
-
2r
-
-
PLL_REF_CLOCK_ENABLED
-
Indicates if the PLL reference clock for the PL interface is enabled.
-
-
-
-
-
-
1r
-
-
DB1_CLOCK_ENABLED
-
Indicates if a clock is forwarded to DB 1.
-
-
-
-
-
-
0r
-
-
DB0_CLOCK_ENABLED
-
Indicates if a clock is forwarded to DB 0.
-
-
-
-
-
-
-
-
-
-
-
PS_CPLD_BASE_REGS
- Basic registers containing version and capabilites information.
-
This register is defined in HDL source file ps_cpld_regs.v.
-
-
-
-
-
-This register returns (in YYMMDDHH format) the oldest revision
- that is still compatible with this one. Compatible means that
- registers or register bits may have been added, but not
- modified or deleted (see OLDEST_CPLD_REVISION of CONSTANTS_REGMAP).
-
-
This register is defined in HDL source file ps_power_regs.v.
-
-
-
-
-
-Controls the power supplies for the iPass connectors.
-
-
-
-
-
Bits
Name
-
-
-
31r
-
-
IPASS_POWER_FAULT1
-
Asserted signal indicates a power fault in power switch for iPass
- connector 1. Sticky bit. Asserted on occurrence. Reset using
- IPASS_CLEAR_POWER_FAULT1.
Asserted signal indicates a power fault in power switch for iPass
- connector 0. Sticky bit. Asserted on occurrence. Reset using
- IPASS_CLEAR_POWER_FAULT0.
This window is defined in HDL source file uhd_regs.v.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RADIO_CTRLPORT_REGMAP
-
-
RADIO_CTRLPORT_WINDOWS
- Each radio's CtrlPort peripheral interface is divided into the
- following memory spaces. Note that the CtrlPort peripheral interface
- starts at offset 0x80000 in the RFNoC Radio block's register space.
- The following diagram displays the distribution of the CtrlPort
- interface to the different modules it interacts with.
-
-
-
-
This window is defined in HDL source file x4xx_core_common.v.
-
-
-
-
-
-Register space reserved for configuring a digital interface over the GPIO lines.
- Currently, SPI is the only supported protocol.
-
-
-
-
-
-
-
-
-
-
-
-
RECONFIG_REGMAP
-
-
RECONFIG_REGS
- These registers are used to upload and verify a new primary image to the
- Max 10 FPGA on-chip flash when configured to support dual configuration
- images. The steps below outline the process of verifying/preparing the
- new image to be written, erasing the current image, writing the new
- image, and verifying the new image was successfully written.
-
Prepare the data...
-
The Max 10 FPGA build should generate a *cfm0_auto.rpd
- file The *.rpd file is a "raw programming
- data" file holding all data related to the
- configuration image (CFM0). There are two
- important items to note regarding the addresses.
- First the *rpd data uses byte addresses.
- Second, the start/end addresses defined by
- FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses
-
As a sanity check, verify the size of the raw
- programming data for CFM0 correspond to the address
- range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by
- reading the values from FLASH_CFM0_START_ADDR_REG and
- FLASH_CFM0_END_ADDR, subtract both values, add one and
- multiply by four.
-
-
Having passed the sanity check the *.rpd data must
- now be manipulated into the form required by Altera's
- on-chip flash IP. Two operations must be performed.
- First the data must be converted from bytes to 32-bit
- words. Second the bit order must be reversed. This is
- illustrated in in the following table which shows byte
- address and data from the *.rpd file compared to the
- word address and data to be written to the on-chip
- flash.
-
-
.Map Addr
.Map Data
Flash Addr
Flash Data
-
0x2B800
0x01
0xAC00
0x8040C020
-
0x2B801
0x02
-
0x2B802
0x03
-
0x2B803
0x04
-
0x2B804
0x05
0xAC01
0xA060E010
-
0x2B805
0x06
-
0x2B806
0x07
-
0x2B807
0x08
-
-
-
The resulting set of flash address data pairs should
- be used when writing FLASH_ADDR_REG and
- FLASH_WRITE_DATA_REG to update the CFM0 image.
- However, prior to writing the new image the old image
- must be erased.
-
-
-
-
Erase the current primary flash image...
-
Read FLASH_STATUS_REG and verify no error bits are
- asserted and that all read, write, and erase operations
- are idle.
-
Disable write protection of the flash by strobing the
- FLASH_DISABLE_WP_STB bit of FLASH_CONTROL_REG.
-
-
Verify write protection is disabled and no errors are
- present by reading FLASH_STATUS_REG.
-
Initiate the erase operation by setting
- FLASH_ERASE_SECTOR and strobing FLASH_ERASE_STB of
- FLASH_CONTROL_REG.
-
Poll the FLASH_ERASE_IDLE bit of
- FLASH_STATUS_REG until it de-asserts indicating the
- erase operation is complete, then verify the operation
- was successful by checking that the FLASH_ERASE_ERR
- bit is de-asserted. Erase operations are expected to
- take a maximum of 350 msec. Upon completion of the erase
- operation write protection will remain disabled.
-
-
Erase additional sectors as required (see
- FLASH_ERASE_SECTOR for details) by restarting with first
- step.
-
-
-
Write the new primary flash image...
-
Read FLASH_STATUS_REG and verify no error bits are
- asserted, all read, write, and erase operations are
- idle, and write protection is disabled.
-
Set the target address for the write to the Max 10
- on-chip flash by writing value from
- FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.
-
Set the data to be written to this address by writing
- the new 32-bit word of the new image to
- FLASH_WRITE_DATA_REG.
-
Initiate the write by strobing FLASH_WRITE_STB of
- FLASH_CONTROL_REG.
-
Poll the FLASH_WRITE_IDLE bit of
- FLASH_STATUS_REG until it de-asserts indicating the
- write operation is complete, then verify the operation
- was successful by checking that the FLASH_WRITE_ERR
- bit is de-asserted. Write operations are expected to
- take a maximum of 550 usec.
-
Upon completion of the write operation return to step
- 2, incrementing the target address by one, and writing
- the next 32-bit word to Max10FlashWriteDatReg. If this
- was the last write, indicated by writing to
- FLASH_PRIMARY_IMAGE_END_ADDR, proceed to the next step
- to enable write protection.
-
After writing the new image enable write protection
- by strobing the FLASH_ENABLE_WP_STB bit of
- FLASH_CONTROL_REG.
-
-
-
Verify the new primary flash image...
-
Read FLASH_STATUS_REG and verify no error bits are
- asserted and that all read, write, and erase operations
- are idle.
-
Set the target address for the read in the Max 10
- on-chip flash by writing value from
- FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.
-
Initiate the read by strobing FLASH_READ_STB of
- FLASH_CONTROL_REG.
-
Poll the FLASH_READ_IDLE bit of
- FLASH_STATUS_REG until it de-asserts indicating the
- read operation is complete, then verify the operation
- was successful by checking that the FLASH_READ_ERR
- bit is de-asserted. There is no guidance on exactly how
- long reads take to complete, but they are expected to be
- fairly quick. A very conservative timeout on this
- polling would be similar to that used for write
- operations.
-
Upon completion of the read operation the resulting
- data returned by the on-chip flash will be available in
- Max10FlashReadDatReg. Read this register, compare to
- expected value previously written, and ensure they
- match.
-
Return to step 2, incrementing the target
- address by one. If this was the last read verification
- is complete and no further action is required.
-
-
-
After the flash has been erased, programmed, and verified, a power
- cycle is required for the new image to become active.
-
-
-
-
-
FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration
-These values are the start and end address of the CFM image flash
- sector from Intel's On-Chip Flash IP Generator.
- Be aware that three different values exist per each of the two
- supported MAX10 variants: 10M04 and 10M08
- Note that the values given in the IP generator are byte based where
- the values of this enum are U32 based (divided by 4).
-
-
-
-
Value
-
Name
-
-
-
-
-
-
Dec
-
-
Hex
-
-
-
-
-
-
4096
-
-
0x01000
-
-
-
FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04
-
-
-
-
-
-
-
-
8192
-
-
0x02000
-
-
-
FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08
-
-
-
-
-
-
-
-
39936
-
-
0x09C00
-
-
-
FLASH_PRIMARY_IMAGE_START_ADDR_10M04
-
-
-
-
-
-
-
-
44032
-
-
0x0AC00
-
-
-
FLASH_PRIMARY_IMAGE_START_ADDR_10M08
-
-
-
-
-
-
-
-
75775
-
-
0x127FF
-
-
-
FLASH_PRIMARY_IMAGE_END_ADDR_10M04
-
-
-
-
-
-
-
-
79871
-
-
0x137FF
-
-
-
FLASH_PRIMARY_IMAGE_END_ADDR_10M08
-
-
-
-
-
-
-
-
- This enumerated type is defined in HDL source file reconfig_engine.v.
-
This register is defined in HDL source file reconfig_engine.v.
-
-
-
-
-
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..17
-
-
Reserved
-
-
-
-
-
-
-
16
-
-
FLASH_MEM_INIT_ENABLED
-
This bit is asserted when the flash can hold an image with memory
- initialization.
-
-
-
-
-
-
15..14
-
-
Reserved
-
-
-
-
-
-
-
13
-
-
FLASH_WRITE_ERR
-
This bit is asserted when write operation fails. Clear this error
- by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In
- the event of a write error...
-
the primary configuration image may be corrupted, and
- power cycling the board may result unknown behavior.
-
write protection of the flash will automatically be
- re-enabled.
-
attempts to disable write protection will be ignored.
-
attempts to read/write/erase the flash will be ignored.
-
-
-
-
-
-
12
-
-
FLASH_WRITE_IDLE
-
This bit is de-asserted when a write operation is in progress. Poll
- this bit after strobing the FLASH_WRITE_STB bit of
- FLASH_CONTROL_REG to determine when the write operation has
- completed, then check the FLASH_WRITE_ERR bit to verify the
- operation was successful.
-
-
-
-
-
-
11..10
-
-
Reserved
-
-
-
-
-
-
-
9
-
-
FLASH_ERASE_ERR
-
This bit is asserted when an erase operation fails. Clear this
- error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In
- the event of an erase error...
-
the primary configuration image may be corrupted, and
- power cycling the board may result in unknown behavior.
-
write protection of the flash will automatically be
- re-enabled.
-
attempts to disable write protection will be ignored.
-
attempts to read/write/erase the flash will be ignored.
-
-
-
-
-
-
8
-
-
FLASH_ERASE_IDLE
-
This bit is de-asserted when an erase operation is in progress. Poll
- this bit after strobing the FLASH_ERASE_STB bit of
- FLASH_CONTROL_REG to determine when the erase operation has
- completed, then check the FLASH_ERASE_ERR bit to verify the
- operation was successful.
-
-
-
-
-
-
7..6
-
-
Reserved
-
-
-
-
-
-
-
5
-
-
FLASH_READ_ERR
-
This bit is asserted when a read operation fails. Clear this error
- by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the
- event of a read error...
-
the data in FLASH_READ_DATA_REG is invalid.
-
attempts to disable write protection will be ignored.
-
attempts to read/write/erase the flash will be ignored.
-
-
-
-
-
-
4
-
-
FLASH_READ_IDLE
-
This bit is de-asserted when a read operation is in progress. Poll
- this bit after strobing the FLASH_READ_STB bit of
- FLASH_CONTROL_REG to determine when the read operation has
- completed, then check the FLASH_READ_ERR bit to verify the
- operation was successful.
-
-
-
-
-
-
3..1
-
-
Reserved
-
-
-
-
-
-
-
0
-
-
FLASH_WP_ENABLED
-
This bit is asserted when the flash is write protected and
- de-asserted when write protection is disabled.
-
Write protection must be enabled prior to performing read
- operations.
-
Write protection must be disabled prior to performing write and
- erase operations.
This register is defined in HDL source file reconfig_engine.v.
-
-
-
-
-
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..11
-
-
Reserved
-
-
-
-
-
-
-
10w
-
-
CLEAR_FLASH_ERASE_ERROR_STB (Strobe)
-
Strobe this bit to clear an erase error.
-
-
-
-
-
-
9w
-
-
CLEAR_FLASH_WRITE_ERROR_STB (Strobe)
-
Strobe this bit to clear a write error.
-
-
-
-
-
-
8w
-
-
CLEAR_FLASH_READ_ERROR_STB (Strobe)
-
Strobe this bit to clear a read error.
-
-
-
-
-
-
7..5w
-
-
FLASH_ERASE_SECTOR (Strobe)
-
Defines the sector to be erased. Has to be set latest with the
- write access which starts the erase operation by strobing
- FLASH_ERASE_STB.
- With 10M04 variants, if the flash is configured to support memory
- initialization (see FLASH_MEM_INIT_ENABLED flag) the sectors 2
- to 4 have to be erased. If the flag is not asserted only sector 4
- has to be erased.
- With 10M08 variants, the sectors to be erased are 3 to 5 when
- using memory initialization or only sector 5 otherwise.
-
-
-
-
-
-
4w
-
-
FLASH_ERASE_STB (Strobe)
-
Strobe this bit to erase the primary Max10 configuration image
- (CFM0).
-
Prior to strobing this bit verify no other write or erase
- operations are in progress, write protection is disabled, and no
- error bits are asserted by reading FLASH_STATUS_REG.
-
Attempts to erase the primary image while other write or erase
- operations are in progress will be ignored.
-
Attempts to erase the primary image when write protection is
- enabled will be ignored.
-
Strobing this bit and FLASH_WRITE_STB simultaneously will
- result both the erase and the write operation being ignored, both
- corresponding error bits being set, and write protection being
- re-enabled.
-
After strobing this bit poll the FLASH_ERASE_IDLE and
- FLASH_ERASE_ERR bits of FLASH_STATUS_REG to determine when
- the erase operation is complete and if it was successful.
-
-
-
-
-
-
3w
-
-
FLASH_WRITE_STB (Strobe)
-
Strobe this bit to write the data contained in
- FLASH_WRITE_DATA_REG to the flash address identified in
- FLASH_ADDR_REG.
-
The flash must be erased before writing new data.
-
Prior to strobing this bit verify write protection is
- disabled, no other write or erase operations are in progress, and
- no error bits are asserted by reading FLASH_STATUS_REG.
-
Attempts to write data while other write or erase operations
- are in progress will be ignored.
-
Attempts to write data with write protection enabled will be
- ignored.
-
Strobing this bit and FLASH_ERASE_STB simultaneously will
- result in both the write and erase operation being ignored,
- both corresponding error bits being set, and write protection
- being re-enabled.
-
After strobing this bit poll theMax10FlashWriteIdle and
- FLASH_WRITE_ERR bits of FLASH_STATUS_REG to determine when
- the write operation is complete and if it was successful.
-
-
-
-
-
-
2w
-
-
FLASH_READ_STB (Strobe)
-
Strobe this bit to read data from the flash address identified in
- FLASH_ADDR_REG.
-
Prior to strobing this bit verify no read, write, or erase
- operations are in progress, no error bits are asserted, and
- write protection is enabled by reading FLASH_STATUS_REG.
-
Attempts to read data while other operations are in progress
- or while write protection is disabled will be ignored.
-
After strobing this bit poll the FLASH_READ_IDLE and
- FLASH_READ_ERR bits of FLASH_STATUS_REG to determine when
- the read operation is complete and if it was successful.
-
Upon successful completion the data read from flash will be
- available in FLASH_READ_DATA_REG.
-
-
-
-
-
-
1w
-
-
FLASH_DISABLE_WP_STB (Strobe)
-
Strobe this bit to disable write protection to the section of the
- Max 10 on-chip flash storing the primary configuration image
- (CFM0).
-
Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to
- determine the current state of write protection.
-
Prior to strobing this bit verify no read operations are in
- progress and no error bits are asserted by reading
- FLASH_STATUS_REG.
-
Attempts to disable write protection while a read is in
- progress will be ignored.
-
Attempts to disable write protection will be ignored if
- this bit is strobed simultaneously with either FLASH_READ_STB
- or FLASH_ENABLE_WP_STB.
-
Write protection must be disabled prior to performing erase or
- write operations.
-
Upon completion of erase/write operations write protection
- will remain disabled. When not actively erasing or writing a new
- image write protection should be enabled to avoid data
- corruption.
-
-
-
-
-
-
0w
-
-
FLASH_ENABLE_WP_STB (Strobe)
-
Strobe this bit to enable write protection to the section of the
- Max 10 on-chip flash storing the primary configuration image
- (CFM0).
-
Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to
- determine the current state of write protection.
-
Prior to strobing this bit verify no write or erase operations
- are in progress and no error bits are asserted by reading
- FLASH_STATUS_REG.
-
Attempts to enable write protection while erase or write
- operations are in progress will be ignored.
-
Write protection must be enabled prior to performing
- read operations.
-
Write protection should be enabled after completing
- write or erase operations to prevent data corruption.
This register is defined in HDL source file reconfig_engine.v.
-
-
-
-
-
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..17
-
-
Reserved
-
-
-
-
-
-
-
16..0
-
-
FLASH_ADDR
-
This field holds the target address for the next read or
- write operation. Set this field prior to strobing the
- FLASH_WRITE_STB and FLASH_READ_STB bits of
- FLASH_CONTROL_REG. Valid addresses are defined by the
- FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration.
This register is defined in HDL source file reconfig_engine.v.
-
-
-
-
-
-
-
-
-
-
-
Bits
Name
-
-
-
31..0
-
-
FLASH_CFM0_END_ADDR
-
Last address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM).
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RF_ATR_REGMAP
-
-
RF_ATR_REGISTERS
- Each channel in the FBX daughterboard has 4 switches in its path. 3 of these are HMC849A 2:1
- switches and the last one is a PE42442 4:1 switch. The latter, as well as the enable lines for
- all four switches are not considered time critical controls, and are hence driven by an I/O
- expander controlled via I2C.
- This register map describes how to control the behavior of the 3 HMC849A switches' control lines.
- There are three supported control schemes for these switches:
-
-
ATR Disabled - Single persistent state.
-
Classic ATR - Each channel's switches depend on the transmission state
- of the respective channel.
-
DB State - Each channel's switches depend on the transmission state
- of all channels in this radio.
-
-
-
-
-
RF_SWITCHES_SIZE_TYPE Enumeration
-
-
-
-
-
Value
-
Name
-
-
-
-
-
-
3
-
-
-
RFS_SIZE
-
-
-
-
-
-
-
-
- This enumerated type is defined in HDL source file rf_atr_control.v.
-
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x000000 + i*4
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file rf_atr_control.v.
-It uses RegType RF_ATR_STATE which is defined in HDL source file rf_atr_control.v.
-
-
-
-
-
-Holds the value for the control lines of each channel's switches
- for a particular ATR sate
-Describes switch control behavior for the different ATR states. When RF0_ATR_OPTION
- is set to use the DB states, TX and RX states for RF0-RF3 are
- combined to create a single vector. This creates 256 different
- combinations, each with its own register. When RF0_ATR_OPTION is set to
- classic ATR, the first 4 offsets in this register group will be driven
- in accordance with the state of RF0.
- CLASSIC ATR MAPPING: Idle[RF0: TX=0, RX=0], RX[RF0: TX=0, RX=1,
- TX[RF0: TX=1, RX=0], FDX[RF0: TX=1, RX=1]
-
-
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x000400 + i*4
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file rf_atr_control.v.
-It uses RegType RF_ATR_STATE which is defined in HDL source file rf_atr_control.v.
-
-
-
-
-
-Holds the value for the control lines of each channel's switches
- for a particular ATR sate
-Describes switch control behavior for the different ATR states. When RF1_ATR_OPTION
- is set to use the DB states, TX and RX states for RF0-RF3 are
- combined to create a single vector. This creates 256 different
- combinations, each with its own register. When RF1_ATR_OPTION is set to
- classic ATR, the first 4 offsets in this register group will be driven
- in accordance with the state of RF1.
- CLASSIC ATR MAPPING: Idle[RF1: TX=0, RX=0], RX[RF1: TX=0, RX=1,
- TX[RF1: TX=1, RX=0], FDX[RF1: TX=1, RX=1]
-
-
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x000800 + i*4
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file rf_atr_control.v.
-It uses RegType RF_ATR_STATE which is defined in HDL source file rf_atr_control.v.
-
-
-
-
-
-Holds the value for the control lines of each channel's switches
- for a particular ATR sate
-Describes switch control behavior for the different ATR states. When RF2_ATR_OPTION
- is set to use the DB states, TX and RX states for RF0-RF3 are
- combined to create a single vector. This creates 256 different
- combinations, each with its own register. When RF2_ATR_OPTION is set to
- classic ATR, the first 4 offsets in this register group will be driven
- in accordance with the state of RF2.
- CLASSIC ATR MAPPING: Idle[RF2: TX=0, RX=0], RX[RF2: TX=0, RX=1,
- TX[RF2: TX=1, RX=0], FDX[RF2: TX=1, RX=1]
-
-
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x000C00 + i*4
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file rf_atr_control.v.
-It uses RegType RF_ATR_STATE which is defined in HDL source file rf_atr_control.v.
-
-
-
-
-
-Holds the value for the control lines of each channel's switches
- for a particular ATR sate
-Describes switch control behavior for the different ATR states. When RF3_ATR_OPTION
- is set to use the DB states, TX and RX states for RF0-RF3 are
- combined to create a single vector. This creates 256 different
- combinations, each with its own register. When RF3_ATR_OPTION is set to
- classic ATR, the first 4 offsets in this register group will be driven
- in accordance with the state of RF3.
- CLASSIC ATR MAPPING: Idle[RF3: TX=0, RX=0], RX[RF3: TX=0, RX=1,
- TX[RF3: TX=1, RX=0], FDX[RF3: TX=1, RX=1]
-
-
This register is defined in HDL source file rf_atr_control.v.
-
-
-
-
-
-Controls whether switch control lines use the TX and RX state of
- their respective channel (Classic ATR) or the daughterboard state
- to select which state to use from values set in RF_ATR_STATE registers.
- For each particular bit:
- 0: Use DB state for ATR
- 1: Classic ATR mode.
-
-
This register is defined in HDL source file rf_atr_control.v.
-
-
-
-
-
-Disable ATR Control. DB state 0 will be reflected regardless of the ATR state.
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..8
-
-
Reserved
-
-
-
-
-
-
-
7..4
-
-
Reserved
-
-
-
-
-
-
-
3
-
-
RF3_ATR_DISABLED (initialvalue=0)
-
-
-
-
-
-
-
2
-
-
RF2_ATR_DISABLED (initialvalue=0)
-
-
-
-
-
-
-
1
-
-
RF1_ATR_DISABLED (initialvalue=0)
-
-
-
-
-
-
-
0
-
-
RF0_ATR_DISABLED (initialvalue=0)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RF_SYNC_REGMAP
-
-
RF_SYNC_REGISTERS
- Each channel in the FBX daughterboard has 4 switches in its path. 3 of these are HMC849A 2:1
- switches and the last one is a PE42442 4:1 switch. The latter, as well as the enable lines for
- all four switches are not considered time critical controls, and are hence driven by a
- TCA6416A I/O expander controlled via I2C.
- This register map controls that I/O expander. The first 6 registers in
- this space set the values of the 5 3-pin sync switches and then an
- RFS enable bit. The 2 additional registers trigger a init sequence for
- the expander peripheral and configuring the I/O with the contents of
- the value registers both with a series of I2C commands.
-
-
-
-
IO_EXPANDER_REGISTER_ADRS Enumeration
-This is not a register spaces for this ctrlport interface but
- instead register addresses on the TCA6416A. Therefore, we will just
- define an enum with these addresses so there is no clash with the
- above ctrlport regmap.
-
-
-
-
Value
-
Name
-
-
-
-
-
-
0
-
-
-
IO_EXP_INPUT_PORT0_REG
-
-
-
-
-
-
-
-
1
-
-
-
IO_EXP_INPUT_PORT1_REG
-
-
-
-
-
-
-
-
2
-
-
-
IO_EXP_OUTPUT_PORT0_REG
-
-
-
-
-
-
-
-
3
-
-
-
IO_EXP_OUTPUT_PORT1_REG
-
-
-
-
-
-
-
-
4
-
-
-
IO_EXP_POLARITY_INV0_REG
-
-
-
-
-
-
-
-
5
-
-
-
IO_EXP_POLARITY_INV1_REG
-
-
-
-
-
-
-
-
6
-
-
-
IO_EXP_CONFIG0_REG
-
-
-
-
-
-
-
-
7
-
-
-
IO_EXP_CONFIG1_REG
-
-
-
-
-
-
-
-
- This enumerated type is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
-
This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
-It uses RegType SYNC_SWITCH which is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
-
-
-
-
-
-Sets I/O to control Sync Switch.
-Sets I/O state to control Sync Switch 1.
-
-
This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
-It uses RegType SYNC_SWITCH which is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
-
-
-
-
-
-Sets I/O to control Sync Switch.
-Sets I/O state to control Sync Switch 2.
-
-
This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
-It uses RegType SYNC_SWITCH which is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
-
-
-
-
-
-Sets I/O to control Sync Switch.
-Sets I/O state to control Sync Switch 3.
-
-
This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
-It uses RegType SYNC_SWITCH which is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
-
-
-
-
-
-Sets I/O to control Sync Switch.
-Sets I/O state to control Sync Switch 4.
-
-
This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
-It uses RegType SYNC_SWITCH which is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
-
-
-
-
-
-Sets I/O to control Sync Switch.
-Sets I/O state to control Sync Switch 5.
-
-
This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
-
-
-
-
-
-Write to this register to trigger I/O configuration I2C sequence of
- TCA6416A I/O expander peripheral.
- Read from this register to check the status of reconfiguring the setup.
-
-
This window is defined in HDL source file x440_rfdc_regs.v.
-
-
-
-
-
-Register space for controlling the data clock MMCM instance
- within the RFDC block design.
- Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the
- regiter space description in chapter 2.
- (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)
-
-
This register is defined in HDL source file x440_rfdc_regs.v.
-It uses RegType RF_RESET_CONTROL_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-Control register for the RF reset controller.
- Verify the FSM ID before polling starting any reset sequence.
- To use the SW reset triggers: Wait until DB*_DONE is de-asserted.
- Assert either the *_RESET or *_ENABLE bitfields.
- Wait until DB*_DONE is asserted to release the trigger.
- The DB*_DONE signal should then de-assert.
- Note: The *_DB1 constants are not used in the HDL, their purpose is
- merely for documentation.
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..10
-
-
Reserved
-
-
-
-
-
-
-
9
-
-
DAC_ENABLE
-
Write a '1' to this bit to trigger the enable sequence for
- the daughterboard 0 DAC chain. Write a '0' once
- db0_dac_seq_done is asserted.
-
-
-
-
-
-
8
-
-
DAC_RESET
-
Write a '1' to this bit to trigger a reset for the
- daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done
- is asserted.
-
-
-
-
-
-
7..6
-
-
Reserved
-
-
-
-
-
-
-
5
-
-
ADC_ENABLE
-
Write a '1' to this bit to trigger the enable sequence for
- the daughterboard 0 ADC chain. Write a '0' once
- db0_adc_seq_done is asserted.
-
-
-
-
-
-
4
-
-
ADC_RESET
-
Write a '1' to this bit to trigger a reset for the
- daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done
- is asserted.
-
-
-
-
-
-
3..1
-
-
Reserved
-
-
-
-
-
-
-
0
-
-
FSM_RESET
-
Write a '1' to this bit to reset the RF reset controller.
- Write a '0' once db0_fsm_reset_done asserts.
This register is defined in HDL source file x440_rfdc_regs.v.
-It uses RegType RF_RESET_STATUS_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-Status register for the RF reset controller.
- Verify the FSM ID before polling starting any reset sequence.
- Refer to RF*_RESET_CONTROL_REG for instructions on how to use
- the status bits in this register.
- Note: The *_DB1 constants are not used in the HDL, their purpose is
- merely for documentation.
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..12
-
-
Reserved
-
-
-
-
-
-
-
11
-
-
DAC_SEQ_DONE
-
This bit asserts ('1') when the DB0 DAC chain reset sequence
- is completed. The bitfield deasserts ('0') after
- deasserting the issued triggered (enable or reset).
-
-
-
-
-
-
10..8
-
-
Reserved
-
-
-
-
-
-
-
7
-
-
ADC_SEQ_DONE
-
This bit asserts ('1') when the DB0 ADC chain reset sequence
- is completed. The bitfield deasserts ('0') after
- deasserting the issued triggered (enable or reset).
-
-
-
-
-
-
6..4
-
-
Reserved
-
-
-
-
-
-
-
3
-
-
FSM_RESET_DONE
-
This bit asserts ('1') when the DB0 RF reset controller FSM
- reset sequence is completed. The bitfield deasserts ('0')
- after deasserting db0_fsm_reset.
This register is defined in HDL source file x440_rfdc_regs.v.
-It uses RegType RF_RESET_CONTROL_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-Control register for the RF reset controller.
- Verify the FSM ID before polling starting any reset sequence.
- To use the SW reset triggers: Wait until DB*_DONE is de-asserted.
- Assert either the *_RESET or *_ENABLE bitfields.
- Wait until DB*_DONE is asserted to release the trigger.
- The DB*_DONE signal should then de-assert.
- Note: The *_DB1 constants are not used in the HDL, their purpose is
- merely for documentation.
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..10
-
-
Reserved
-
-
-
-
-
-
-
9
-
-
DAC_ENABLE
-
Write a '1' to this bit to trigger the enable sequence for
- the daughterboard 0 DAC chain. Write a '0' once
- db0_dac_seq_done is asserted.
-
-
-
-
-
-
8
-
-
DAC_RESET
-
Write a '1' to this bit to trigger a reset for the
- daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done
- is asserted.
-
-
-
-
-
-
7..6
-
-
Reserved
-
-
-
-
-
-
-
5
-
-
ADC_ENABLE
-
Write a '1' to this bit to trigger the enable sequence for
- the daughterboard 0 ADC chain. Write a '0' once
- db0_adc_seq_done is asserted.
-
-
-
-
-
-
4
-
-
ADC_RESET
-
Write a '1' to this bit to trigger a reset for the
- daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done
- is asserted.
-
-
-
-
-
-
3..1
-
-
Reserved
-
-
-
-
-
-
-
0
-
-
FSM_RESET
-
Write a '1' to this bit to reset the RF reset controller.
- Write a '0' once db0_fsm_reset_done asserts.
This register is defined in HDL source file x440_rfdc_regs.v.
-It uses RegType RF_RESET_STATUS_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-Status register for the RF reset controller.
- Verify the FSM ID before polling starting any reset sequence.
- Refer to RF*_RESET_CONTROL_REG for instructions on how to use
- the status bits in this register.
- Note: The *_DB1 constants are not used in the HDL, their purpose is
- merely for documentation.
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..12
-
-
Reserved
-
-
-
-
-
-
-
11
-
-
DAC_SEQ_DONE
-
This bit asserts ('1') when the DB0 DAC chain reset sequence
- is completed. The bitfield deasserts ('0') after
- deasserting the issued triggered (enable or reset).
-
-
-
-
-
-
10..8
-
-
Reserved
-
-
-
-
-
-
-
7
-
-
ADC_SEQ_DONE
-
This bit asserts ('1') when the DB0 ADC chain reset sequence
- is completed. The bitfield deasserts ('0') after
- deasserting the issued triggered (enable or reset).
-
-
-
-
-
-
6..4
-
-
Reserved
-
-
-
-
-
-
-
3
-
-
FSM_RESET_DONE
-
This bit asserts ('1') when the DB0 RF reset controller FSM
- reset sequence is completed. The bitfield deasserts ('0')
- after deasserting db0_fsm_reset.
This register is defined in HDL source file x440_rfdc_regs.v.
-It uses RegType RF_AXI_STATUS_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-Status register for the RF AXI-Stream interfaces.
- Note: The *_DB1 constants are not used in the HDL, their purpose is
- merely for documentation.
-
-
-
-
-
-
Bits
Name
-
-
-
31..30
-
-
USER_ADC_TREADY_DB1
-
This bitfield is wired to the user's ADC (DB1) AXI-Stream
- TReady handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
29..28
-
-
USER_ADC_TVALID_DB1
-
This bitfield is wired to the user's ADC (DB1) AXI-Stream
- TValid handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
27..26
-
-
RFDC_ADC_I_TVALID_DB1
-
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
- TValid handshake signals (I portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
25..24
-
-
RFDC_ADC_Q_TVALID_DB1
-
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
- TValid handshake signals (Q portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
23..22
-
-
RFDC_ADC_I_TREADY_DB1
-
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
- TReady handshake signals (I portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
21..20
-
-
RFDC_ADC_Q_TREADY_DB1
-
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
- TReady handshake signals (Q portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
19..18
-
-
RFDC_DAC_TVALID_DB1
-
This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
- TValid handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
17..16
-
-
RFDC_DAC_TREADY_DB1
-
This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
- TReady handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
15..14
-
-
USER_ADC_TREADY
-
This bitfield is wired to the user's ADC (DB0) AXI-Stream
- TReady handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
13..12
-
-
USER_ADC_TVALID
-
This bitfield is wired to the user's ADC (DB0) AXI-Stream
- TValid handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
11..10
-
-
RFDC_ADC_I_TVALID
-
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
- TValid handshake signals (I portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
9..8
-
-
RFDC_ADC_Q_TVALID
-
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
- TValid handshake signals (Q portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
7..6
-
-
RFDC_ADC_I_TREADY
-
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
- TReady handshake signals (I portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
5..4
-
-
RFDC_ADC_Q_TREADY
-
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
- TReady handshake signals (Q portion). The LSB is channel 0
- and the MSB is channel 1.
-
-
-
-
-
-
3..2
-
-
RFDC_DAC_TVALID
-
This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
- TValid handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
-
-
-
-
-
-
1..0
-
-
RFDC_DAC_TREADY
-
This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
- TReady handshake signals. The LSB is channel 0 and the MSB
- is channel 1.
This register is defined in HDL source file x440_rfdc_regs.v.
-It uses RegType FABRIC_DSP_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-This register provides information to the driver on the type
- of DSP that is instantiated in the fabric.
- The X410 platform supports multiple RF daughterboards, each requiring
- a different fabric RF DSP chain that works with specific RFDC settings.
- Each bandwidth DSP chain has a unique identifier (BW in MHz), this
- information is conveyed in this register to let the driver
- configure the RFDC with the proper settings.
- Also, channel count for the DSP module is included.
- Note: The *_DB1 constants are not used in the HDL, their purpose is
- merely for documentation.
-
-
-
This register is defined in HDL source file x440_rfdc_regs.v.
-
-
-
-
-
-This register enables calibration data in the DAC data path for each of the
- four channels. Each of these bits is normally '0'. When written '1', DAC data
- for the corresponding channel will be constantly driven with the contents of
- the CALIBRATION_DATA register.
-
-
This register is defined in HDL source file x440_rfdc_regs.v.
-
-
-
-
-
-This register shows threshold status for the ADCs. Each bit reflects the
- RFDC's real-time ADC status signals, which will assert when the ADC input
- signal exceeds the programmed threshold value. The status will remain
- asserted until cleared by software.
- The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is
- the location of the tile in the converter column and ZZ is either 01 (the
- lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
- See also the Xilinx document PG269.
-
-
This register is defined in HDL source file x440_rfdc_regs.v.
-It uses RegType ADC_TILEMAP_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-This register describes how the ADCs map to the respective tiles. It
- lets us designate an ADC as channel 0, channel 1, etc. depending on
- how those channels are externally connected to the RFSoC.
-
- For every channel, this register stores the tile number and the block
- number of the converter. This can be used to then address the correct
- converter in the various Xilinx interfaces/APIs.
-
-
-
-
-
-
Bits
Name
-
-
-
31..30
-
-
ADC_TILEMAP_DB1_CHAN3_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 3, daughterboard 1.
-
-
-
-
-
-
29..28
-
-
ADC_TILEMAP_DB1_CHAN3_TILE (initialvalue=0)
-
Tile number of the ADC for channel 3, daughterboard 1.
-
-
-
-
-
-
27..26
-
-
ADC_TILEMAP_DB1_CHAN2_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 2, daughterboard 1.
-
-
-
-
-
-
25..24
-
-
ADC_TILEMAP_DB1_CHAN2_TILE (initialvalue=0)
-
Tile number of the ADC for channel 2, daughterboard 1.
-
-
-
-
-
-
23..22
-
-
ADC_TILEMAP_DB1_CHAN1_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 1, daughterboard 1.
-
-
-
-
-
-
21..20
-
-
ADC_TILEMAP_DB1_CHAN1_TILE (initialvalue=0)
-
Tile number of the ADC for channel 1, daughterboard 1.
-
-
-
-
-
-
19..18
-
-
ADC_TILEMAP_DB1_CHAN0_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 0, daughterboard 1.
-
-
-
-
-
-
17..16
-
-
ADC_TILEMAP_DB1_CHAN0_TILE (initialvalue=0)
-
Tile number of the ADC for channel 0, daughterboard 1.
-
-
-
-
-
-
15..14
-
-
ADC_TILEMAP_DB0_CHAN3_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 3, daughterboard 0.
-
-
-
-
-
-
13..12
-
-
ADC_TILEMAP_DB0_CHAN3_TILE (initialvalue=0)
-
Tile number of the ADC for channel 3, daughterboard 0.
-
-
-
-
-
-
11..10
-
-
ADC_TILEMAP_DB0_CHAN2_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 2, daughterboard 0.
-
-
-
-
-
-
9..8
-
-
ADC_TILEMAP_DB0_CHAN2_TILE (initialvalue=0)
-
Tile number of the ADC for channel 2, daughterboard 0.
-
-
-
-
-
-
7..6
-
-
ADC_TILEMAP_DB0_CHAN1_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 1, daughterboard 0.
-
-
-
-
-
-
5..4
-
-
ADC_TILEMAP_DB0_CHAN1_TILE (initialvalue=0)
-
Tile number of the ADC for channel 1, daughterboard 0.
-
-
-
-
-
-
3..2
-
-
ADC_TILEMAP_DB0_CHAN0_BLOCK (initialvalue=0)
-
Block number (within the tile) of the ADC for channel 0, daughterboard 0.
-
-
-
-
-
-
1..0
-
-
ADC_TILEMAP_DB0_CHAN0_TILE (initialvalue=0)
-
Tile number of the ADC for channel 0, daughterboard 0.
This register is defined in HDL source file x440_rfdc_regs.v.
-It uses RegType DAC_TILEMAP_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-This register describes how the DACs map to the respective tiles. It
- lets us designate an DAC as channel 0, channel 1, etc. depending on
- how those channels are externally connected to the RFSoC.
-
- For every channel, this register stores the tile number and the block
- number of the converter. This can be used to then address the correct
- converter in the various Xilinx interfaces/APIs.
-
-
-
-
-
-
Bits
Name
-
-
-
31..30
-
-
DAC_TILEMAP_DB1_CHAN3_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 3, daughterboard 1.
-
-
-
-
-
-
29..28
-
-
DAC_TILEMAP_DB1_CHAN3_TILE (initialvalue=0)
-
Tile number of the DAC for channel 3, daughterboard 1.
-
-
-
-
-
-
27..26
-
-
DAC_TILEMAP_DB1_CHAN2_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 2, daughterboard 1.
-
-
-
-
-
-
25..24
-
-
DAC_TILEMAP_DB1_CHAN2_TILE (initialvalue=0)
-
Tile number of the DAC for channel 2, daughterboard 1.
-
-
-
-
-
-
23..22
-
-
DAC_TILEMAP_DB1_CHAN1_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 1, daughterboard 1.
-
-
-
-
-
-
21..20
-
-
DAC_TILEMAP_DB1_CHAN1_TILE (initialvalue=0)
-
Tile number of the DAC for channel 1, daughterboard 1.
-
-
-
-
-
-
19..18
-
-
DAC_TILEMAP_DB1_CHAN0_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 0, daughterboard 1.
-
-
-
-
-
-
17..16
-
-
DAC_TILEMAP_DB1_CHAN0_TILE (initialvalue=0)
-
Tile number of the DAC for channel 0, daughterboard 1.
-
-
-
-
-
-
15..14
-
-
DAC_TILEMAP_DB0_CHAN3_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 3, daughterboard 0.
-
-
-
-
-
-
13..12
-
-
DAC_TILEMAP_DB0_CHAN3_TILE (initialvalue=0)
-
Tile number of the DAC for channel 3, daughterboard 0.
-
-
-
-
-
-
11..10
-
-
DAC_TILEMAP_DB0_CHAN2_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 2, daughterboard 0.
-
-
-
-
-
-
9..8
-
-
DAC_TILEMAP_DB0_CHAN2_TILE (initialvalue=0)
-
Tile number of the DAC for channel 2, daughterboard 0.
-
-
-
-
-
-
7..6
-
-
DAC_TILEMAP_DB0_CHAN1_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 1, daughterboard 0.
-
-
-
-
-
-
5..4
-
-
DAC_TILEMAP_DB0_CHAN1_TILE (initialvalue=0)
-
Tile number of the DAC for channel 1, daughterboard 0.
-
-
-
-
-
-
3..2
-
-
DAC_TILEMAP_DB0_CHAN0_BLOCK (initialvalue=0)
-
Block number (within the tile) of the DAC for channel 0, daughterboard 0.
-
-
-
-
-
-
1..0
-
-
DAC_TILEMAP_DB0_CHAN0_TILE (initialvalue=0)
-
Tile number of the DAC for channel 0, daughterboard 0.
This register is defined in HDL source file x440_rfdc_regs.v.
-It uses RegType RFDC_INFO_REGTYPE which is defined in HDL source file common_regs.v.
-
-
-
-
-
-This register provides information about how the RFDC is connected to
- the rest of the fabric.
- Specifically, between the actual RFDC and the RFNoC infrastructure,
- there may be additional resampling (if the RFDC resampler cannot handle
- all the resampling itself) and it is important to know how wide the
- connection from the RFDC gearbox FIFO to the rest of the design is.
- Note: The *_DB1 constants are not used in the HDL, their purpose is
- merely for documentation.
-
-
-
-
-
-
Bits
Name
-
-
-
31..26
-
-
Reserved
-
-
-
-
-
-
-
25..23
-
-
RFDC_INFO_SPC_TX_DB1 (initialvalue=1)
-
Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 1.
-
-
-
-
-
-
22..20
-
-
RFDC_INFO_SPC_RX_DB1 (initialvalue=1)
-
Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 1.
-
-
-
-
-
-
19..16
-
-
RFDC_INFO_XTRA_RESAMP_DB1 (initialvalue=1)
-
Additional resampling happening outside the RFDC for daughterboard 0.
-
-
-
-
-
-
15..10
-
-
Reserved
-
-
-
-
-
-
-
9..7
-
-
RFDC_INFO_SPC_TX (initialvalue=1)
-
Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 0.
-
-
-
-
-
-
6..4
-
-
RFDC_INFO_SPC_RX (initialvalue=1)
-
Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 0.
-
-
-
-
-
-
3..0
-
-
RFDC_INFO_XTRA_RESAMP (initialvalue=1)
-
Additional resampling happening outside the RFDC for daughterboard 0.
This register is defined in HDL source file rfdc_timing_control.v.
-
-
-
-
-
-Gearbox reset control register.
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
Reserved
-
-
-
-
-
-
-
23..16
-
-
Reserved
-
-
-
-
-
-
-
15..8
-
-
Reserved
-
-
-
-
-
-
-
7..2
-
-
Reserved
-
-
-
-
-
-
-
1w
-
-
DAC_RESET (Strobe)
-
This reset is for the gearbox on the DAC data path that is used to
- move data from one clock domain to another outside the RFDC. Write
- a 1 to this bit to send a reset pulse to the DAC gearbox.
-
-
-
-
-
-
0w
-
-
ADC_RESET (Strobe)
-
This reset is for the gearbox on the ADC data path that is used to
- move data from one clock domain to another outside the RFDC. Write
- a 1 to this bit to send a reset pulse to the ADC gearbox.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI_REGMAP
-
-
-
SPI_REGS
-
-
This register map is present for each SPI master.
-
For information about the register content and the way to interact with the core see the
-documentation
-of the SPI master from opencores used internally.
-
The core is configured to operate with 16 slave signal signals, up to 128 bits per transmission and 8 bit clock divider.
-Only 64 bits of data are available via this register interface.
-
For the different SPI modes use the following table to derive the bits in CONTROL register. Only option 0 (CPOL=0, CPHA=0) has been tested.
This register is defined in HDL source file uhd_regs.v.
-
-
-
-
-
-
-
-
-
-
-
-
Bits
Name
-
-
-
31..16
-
-
pause_clear
-
-
If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause.
-Pause clear must be less than pause set or terrible things will happen.
-The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only
-used with 100Gb ethernet
-
-
-
-
-
-
15..0
-
-
pause_set
-
-
If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only
-used with 100Gb ethernet
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VERSIONING_REGS_REGMAP
-
-
VERSIONING_CONSTANTS
-
-
-
-
-
CPLD_IFC_VERSION Enumeration
-CPLD interface module.
- For guidance on when to update these revision numbers,
- please refer to the register map documentation accordingly:
-
- This enumerated type is defined in HDL source file cpld_interface_regs.v.
-
-
-
-
-
-
-
-
DB_GPIO_IFC_VERSION Enumeration
-Daughterboard GPIO interface.
- For guidance on when to update these revision numbers,
- please refer to the register map documentation accordingly:
-
- This enumerated type is defined in HDL source file rf_core_full.v.
-
-
-
-
-
-
-
VERSIONING_REGS
-
-
-
-
-
COMPONENTS_INDEXES Enumeration
-This enum contains indexes for all the components in the X410
- (both common and app-specific) which version information is
- desired to be available for compatibility tracking purposes.
-
-
Description
Index range
Max # of components
-
Common components
0 to 23
24
-
UHD-specific components
24 to 43
20
-
LV-specific components
44 to 63
20
-
-
-
-
-
Value
-
Name
-
-
-
-
-
-
0
-
-
-
FPGA_VERSION_INDEX
-
-
-
-
-
-
-
-
1
-
-
-
CPLD_IFC_INDEX
-
-
-
-
-
-
-
-
2
-
-
-
DB0_RF_CORE_INDEX
-
-
-
-
-
-
-
-
3
-
-
-
DB1_RF_CORE_INDEX
-
-
-
-
-
-
-
-
4
-
-
-
DB0_GPIO_IFC_INDEX
-
-
-
-
-
-
-
-
5
-
-
-
DB1_GPIO_IFC_INDEX
-
-
-
-
-
-
-
-
- This enumerated type is defined in HDL source file x4xx_versioning_regs.v.
-
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x10000A0C00 + i*0x10
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file x4xx_versioning_regs.v.
-It uses RegType VERSION_TYPE which is defined in HDL source file x4xx_versioning_regs.v.
-
-
-
-
-
-Component's current version.
- This register contains the current component's version implemented in HDL.
- The current version shall be used to detect a component being too
- old for the driver/software:
- SW oldest compatible version > Component's current version --> Component is too old.
-
-
-
-
-
Bits
Name
-
-
-
31..23
-
-
MAJOR (initialvalue=0)
-
Major number (max = 511): an increase reflects a breaking change.
- IMPORTANT!MAJOR must always remain in sync between the component's
- CURRENT_VERSION and OLDEST_COMPATIBLE_VERSION registers.
a new feature is added to the component, which does not conflict with the driver.
-
minor implementation changes were made to the component which are worth tracking.
-
the component has added new bitfields/registers that do not require software interaction
- (i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to
- previously undefined bits).
-
Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
- but that should not impact the component's behavior
- Eventually, this number is intended to be automatically incremented for any new build.
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x10000A0C04 + i*0x10
-
-
-
-
-
-
-
-
-
-
-
Initial Values
-
-
default
=>
0x00000000
-
-
-
-
This register is defined in HDL source file x4xx_versioning_regs.v.
-It uses RegType VERSION_TYPE which is defined in HDL source file x4xx_versioning_regs.v.
-
-
-
-
-
-Component's oldest compatible version.
- This register contains the oldest compatible component's version, that is the oldest
- component's implementation that is compatible with the current implementation.
- The oldest compatible version shall be used to detect a component being too
- new for the driver/software:
- SW current version < Component's oldest compatible version --> Component is too new.
-
-
-
-
-
Bits
Name
-
-
-
31..23
-
-
MAJOR (initialvalue=0)
-
Major number (max = 511): an increase reflects a breaking change.
- IMPORTANT!MAJOR must always remain in sync between the component's
- CURRENT_VERSION and OLDEST_COMPATIBLE_VERSION registers.
a new feature is added to the component, which does not conflict with the driver.
-
minor implementation changes were made to the component which are worth tracking.
-
the component has added new bitfields/registers that do not require software interaction
- (i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to
- previously undefined bits).
-
Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
- but that should not impact the component's behavior
- Eventually, this number is intended to be automatically incremented for any new build.
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x10000A0C08 + i*0x10
-
-
-
-
-
-
-
-
-
-
-
Initial Value not specified
-
-
-
This register is defined in HDL source file x4xx_versioning_regs.v.
-It uses RegType TIMESTAMP_TYPE which is defined in HDL source file x4xx_versioning_regs.v.
-
-
-
-
-
-Component's versions update time.
- This register provides the time stamp for the last modification to
- the component's versions (current & oldest compatible).
- The time stamp is provided in hexadecimal format: 0xYYMMDDHH.
-
-
-
-
-
-
Bits
Name
-
-
-
31..24
-
-
YY
-
This is the year number after 2000 (e.g. 2019 = 0x19).
-
-
-Cannot determine accessibility through this path
-
-Total Offset =
-
0x10000A0C0C + i*0x10
-
-
-
-
-
-
-
-
-
-
-
Initial Value not specified
-
-
-
This register is defined in HDL source file x4xx_versioning_regs.v.
-It uses RegType RESERVED_TYPE which is defined in HDL source file x4xx_versioning_regs.v.
-
-
-
-
-
-Reserved.
-
-
-
-
-
-
-
-
-
-
-
-
-
XGE_MAC_REGMAP
-
-
-
OPENCORE_XGE_REGISTERS
-
-
10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf
-
-
-
-
-
-
\ No newline at end of file
diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/common_regs.v b/top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/common_regs.v
index 1fe18da..9a66d9a 100644
--- a/top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/common_regs.v
+++ b/top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/common_regs.v
@@ -71,6 +71,9 @@
//
//
//
+//
+// AXI_HPC0_WINDOW AXI_HPC1_WINDOW
+//
//
// This is a regmap to document the different ports that have access to the PS system memory.
// Each port may have different restrictions on system memory. See the corresponding window
diff --git a/top/x400/regmap/x410/versioning_regs_regmap_utils.vh b/top/x400/regmap/x410/versioning_regs_regmap_utils.vh
index 06b14d7..259a574 100644
--- a/top/x400/regmap/x410/versioning_regs_regmap_utils.vh
+++ b/top/x400/regmap/x410/versioning_regs_regmap_utils.vh
@@ -83,9 +83,9 @@
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
- localparam FPGA_CURRENT_VERSION_MAJOR = 'h9; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
- localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h9; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
- localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h25020611; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
+ localparam FPGA_CURRENT_VERSION_MAJOR = 'hA; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
+ localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'hA; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
+ localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h25031309; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_100M_VERSION
localparam RF_CORE_100M_VERSION_SIZE = 7;
diff --git a/top/x400/regmap/x440/versioning_regs_regmap_utils.vh b/top/x400/regmap/x440/versioning_regs_regmap_utils.vh
index ef9a713..9d9ef92 100644
--- a/top/x400/regmap/x440/versioning_regs_regmap_utils.vh
+++ b/top/x400/regmap/x440/versioning_regs_regmap_utils.vh
@@ -83,9 +83,9 @@
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
- localparam FPGA_CURRENT_VERSION_MAJOR = 'h9; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
- localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h9; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
- localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h25020611; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
+ localparam FPGA_CURRENT_VERSION_MAJOR = 'hA; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
+ localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'hA; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
+ localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h25031309; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_FULL_VERSION
localparam RF_CORE_FULL_VERSION_SIZE = 7;
diff --git a/top/x400/x4xx.sv b/top/x400/x4xx.sv
index 4ac0336..dfad66b 100644
--- a/top/x400/x4xx.sv
+++ b/top/x400/x4xx.sv
@@ -3116,13 +3116,13 @@ endmodule
//
+
+ 
+ Make sure the GPIO lines between FPGA and GPIO board are not driven by
+ two drivers. Set the DIO registers in PS_CPLD_BASE_REGMAP appropriately.
+
+
+